I n my design C6455 communication with FPGA using emifa,in Synchronous mode.
emifa clock rate is set to 125M,provided by DSP.
when I read or write from FPGA, we or oe signal is not Continuous, then the communication rate cannot reach 125M, why?
Are you saying that WE and OE do not follow the timing diagram shown in Figures 17 & 18 in the EMIF User's Guide?
Or are you saying that WE and OE go high at the end of a burst, similar to what is shown in those figures?
How wide is the data bus on this interface to your FPGA?
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