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Digital Signal Processors (DSP)
C6000 Single Core DSP
C64x Single Core DSP Forum
c6455 EMIF Cache
I have an FPGA connected to c6455 through EMIF interface.
There is a problem when trying to access an address consecutively.
Is it possible to configure EMIF interface cacheable, and if yes what is the default configuration for it?
Thanks a lot
"Default configuration" varies widely depending on your actual method of configuration.
There are three available cache memories in the C6455, L1P, L2D, and L2. These have a configuration at reset and they also have a configuration based on CSL or BIOS commands and the BIOS configuration or platform files.
In addition, the Memory Attribute Registers (MAR) are used to enable cacheability on specific memory ranges.
All of the registers for configuring the above are described in the C64x+ Megamodule Reference Guide.
Depending on the nature of the information access from or through the FPGA, you may or may not want caching enabled for that region of memory.
Please supply more information on your system, including the versions of CCS and BIOS that you are using and more detail on the FPGA interface and data being accessed.
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