TMS320C6747: EMIF A to 16 bit for UART and SRAM

Part Number: TMS320C6747

Hi,

In our design there is already a connection from C6747 to an UART, starting with both EMA_BA:

EMA_BA[0] to A[0], EMA_BA[1] to A[1], EMA_A[0] to A[2] and so on. This is working.

I want to make a further connection to an SRAM (MT48LC16M8A2) with the same 16 bit data at EMIF A. In SPRUFL6D.EMIF.PDF I can see at page 26, that in case of 16 bit data A[0] should be connected to EMA_BA[1] and A[1] to EMA_A[0] and so on, but there they are talking about asynchronous RAM.

In an example from Spectrum Digital I find an 1-to-1 connection (A[0-12] and BA[0-1]).

I got confused about starting with EMA_BA (one or both bits) or EMA_A[0]. If I must change our existing connection, I'll got in trouble with the existing UART. Hopefully I can connect to the SRAM starting with EMA_BA[0-1] like before, but SPRUFL6D.EMIF.PDF says this is for 8 bit data and asynchronous interfaces.

Kind regards,

Pablo H.

  • Hi Pablo,

    I've notified the C67x team. Their feedback will be posted here.

    Best Regards,
    Yordan

     


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  • Guru 81315 points
    Pablo,

    Welcome to the E2E forum. I hope you will find many good answers posted from past questions, and get good help with your inquiries. The database of helpful information is quite large.

    Do you already have another SDRAM connected to EMIFB? If not, you should put your SDRAM on EMIFB. It was very confusing to me when you called this an SRAM, which is not the common name to use (although technically true in a pure etymology sense, I suppose).

    If you do already have another SDRAM on EMIFB, then you can connect this new one on EMIFA using a different CS line to select it than the CS line used for the UART. Each CS-selected memory space will have its own independent timing and functional configuration so there will be no trouble between the existing devices.

    Regards,
    RandyP

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  • In reply to RandyP:

    Hi Randy,

    many thanks for the fast reply.

    Unfortunately, we have the EMIF B not accessible. We use nearly all GPIOs.

    I don't understand, if connecting an SDRAM with 16 bit I necessarily need to connect as page 26 in SPRUFL6D.EMIF.PDF. That means:

    A[0] - EMA_BA[1]

    A[1] - EMA_A[0]

    What happens if I connect an SDRAM this way (as we have with the UART):

    A[0] - EMA_BA[1]

    A[1] - EMA_BA[0]

    A[2] - EMA_A[0]

    Maybe there is no problem. All of the Micron variants

    MT48LC32M4A2 – 8 Meg x 4 x 4 Banks
    MT48LC16M8A2 – 4 Meg x 8 x 4 Banks
    MT48LC8M16A2 – 2 Meg x 16 x 4 Banks

    show the same address pinning with BA[0], BA[1], A[0], A[1]...

    The connection with both BA pins seems to be due to another interface, this time 8 bit (Anybus). It works well with the other 16 bit interface (UART). So I think, with the SDRAM there will be no problem.

    Kind regards, Pablo

  • Guru 81315 points

    In reply to Pablo Holtkamp:

    Pablo,

    You need to connect the SDRAM as shown on page 15 of SPRUFL6D.

    Regards,
    RandyP

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  • In reply to RandyP:

    Randy,

    I think that now all interfaces are documented in the C6747 TRM - SPRUH91D from Sept 2016:
    http://www.ti.com/lit/ug/spruh91d/spruh91d.pdf

    This would be page 700 Fig 18-3/18.4 and Table 18-6 for address connection.

    A.

  • In reply to AnBer:

    Hi Randy,

    many thanks for your help.

    I have to explain more about our project. It already existed with several adress/data interfaces:

    Anybus with 8 bit data, 2 x UART with 8 bit data and Ethernet controller with 8 bit data.

    At the beginning we had only 8 bit data, therefore we connected both BA pins with A[0] and A[1].

    Last year we changed the ethernet controller to another with 16 bit data. This device (wiznet W5300) can operate in 8 bit and 16 bit mode. It ignores the LSB A[0] when operated in 16 bit mode. Everything works fine.

    With this configuration, we are using 3 of the 5 CS pins for our interfaces.

    And now we want to communicate with an SDRAM, in 16 bit mode.

    SDRAMs need a special connection, as you mentioned. We must reconfigure the EMIF interface, making osolete 2 of our CS pins. Unfortunately, these CS[5] (now RAS) and CS[4] (now CAS) pins are not reconfigurable at other pins. We have to help ourselves with GPIOs.

    I think our problem is solved. Whether it works or not, we will see in a half years time, when we have the new board.

    Now I try to close the case.

    Kind regards, Pablo