C64x Single Core DSP Forum - Recent Threads

c6457 Mcbsp used as SPI doubt

yue zhang2 — Fri, 24 May 2013 02:54:44 GMT

i configured the mcbsp0 on c6457 as spi master, after configer each register, i meet with the problem that when i doesn't set the GRST(in the SPCR register )as 1 for all the time, I can get the signel of FSX, DX,CLKX on oscilloscope which seems normal, and of cause, it doesn't division the frequency,the frequency is too high to use. but when i set the GRST as 1, the signal are all gone, i can get nothing on oscilloscope. i doubt it is because i didn't set the register right, but i follow the step of mcbsp configer as spi grimly. now i don't konw what to do.can anyone helps? thanks very much. Here is my code:#include<stdio.h>
#include<csl.h>
#include<csl_mcbsp.h>
#include<string.h>
#include<csl_chip.h>

CSL_McbspHandle hMcbsp;

#define WAIT_FOR_2_CLK do {                                   \
                            volatile int delayCnt = 2;      \
                            while(delayCnt > 0) --delayCnt; \
                           }while (0)
void DSP_MCBSP_Init()
{

CSL_McbspObj        mcbspObj;
    CSL_Status            status;
    CSL_McbspConfig MyConfig;
    CSL_BitMask16        ctrlMask;
    MyConfig.SPCR=0x02001000;//

    MyConfig.RCR=0x7f050000;//0x00040000;
    MyConfig.XCR=0x00050000;//00010000
    MyConfig.SRGR=0x20001350;//0xb0200150;
    MyConfig.MCR= 0x00000000;
    MyConfig.RCERE0=0x00000000;
    MyConfig.RCERE1=0x00000000;
    MyConfig.RCERE2=0x00000000;
    MyConfig.RCERE3=0x00000000;
    MyConfig.XCERE0=0x00000000;
    MyConfig.XCERE1=0x00000000;
    MyConfig.XCERE2=0x00000000;
    MyConfig.XCERE3=0x00000000;
    MyConfig.PCR=0x00000A0C;//0x00000a0c;

memset (&mcbspObj, 0, sizeof(CSL_McbspObj));

CSL_mcbspInit (NULL);
hMcbsp = CSL_mcbspOpen (&mcbspObj, CSL_MCBSP_0, NULL, &status);
ctrlMask=0;
ctrlMask = CSL_MCBSP_CTRL_RX_DISABLE
                | CSL_MCBSP_CTRL_TX_DISABLE
                | CSL_MCBSP_CTRL_FSYNC_DISABLE   //GAI
                | CSL_MCBSP_CTRL_SRG_DISABLE;       //GAI(5-22 9:16)
     CSL_mcbspHwControl (hMcbsp, CSL_MCBSP_CMD_RESET_CONTROL, &ctrlMask);
     WAIT_FOR_2_CLK;
status = CSL_mcbspHwSetupRaw (hMcbsp, &MyConfig);
WAIT_FOR_2_CLK;

WAIT_FOR_2_CLK;
ctrlMask =0;
hMcbsp->regs->SPCR =0x02E01000;//GRST=1
WAIT_FOR_2_CLK;
hMcbsp->regs->SPCR =0x02401000;
WAIT_FOR_2_CLK;
hMcbsp->regs->SPCR =0x02411001;//XRST=RRST=1
WAIT_FOR_2_CLK;
}
void DSP_MCBSP_Write()
{
int a=5;
while(1)
{
CSL_mcbspWrite (hMcbsp, CSL_MCBSP_WORDLEN_8, &a);

}
}
void main()
{
//int a;
DSP_MCBSP_Init();
DSP_MCBSP_Write();
}

external event trigger edma fail

weslly li — Thu, 23 May 2013 17:08:09 GMT

Hi,

I'm trying to use gpio4 to trigger edma in 6455. Gpio4 event(number 52) was actually latched into ERH(0x00100000), and event enable register(EERH=0x00100000) was set correctly, but seems this event was not pushed into event queue, since ERH remaining set, and no data movement occur.

Any body can give me a hint?

thanks,

Weslly.

mcbsp, spi and ads1274

Manuel Fernandez — Mon, 20 May 2013 22:25:54 GMT

Hello,

I´m using a dsk6455 board and the ADC ads1274evm (5-6k interface board, too) . I use only one channel (ads1274) with protocol spi and it works perfectly, but now I need to use the four channels. I have programmed the RCR register (RFRLEN1) to 4 words, but it doesn't work and I don't know why.

Could you help me, please?

Best regards.

Manuel Fernández Ros

C6455+ NAND flash ??

shine lee1 — Wed, 22 May 2013 02:16:26 GMT

Hello..

Is it possible to use NAND FLASH C6455?

Are there any considerations?

Process technologies

Nick Cheng — Wed, 22 May 2013 09:40:36 GMT

Dear Sir/Madam,

What is the process technology used to fabricate the OMAP-L138, is it purely based on bipolar technology, CMOS, BiCMOS? We will like to know the underlying IC technology.

Next is the component susceptible to Single Event Latch up (LETth)?

Regards,

Nick

C6455 system trace set up

Chao Hu — Fri, 17 May 2013 19:16:24 GMT

Hi,

I'm trying to set up trace/profile for C6455 DSP using spectrum digital XDS560V2 Pro STM emulator. I'm using CCS5.3.

I have done trace/profile for C6678 previsoulsy, so I'm folloing similar procedure. When set up target configuration, for C6678, CSSTM_0 node was automatically added by the tool and all properties are set. But for C6455, there is no such node added by default.

Do I need to add the CSSTM node to the target configuration file? If so, how do I determine its properties, such as port number and address.

Thank you,

Chao

who can explain why using edma can improve algorithms performance

steve nice — Fri, 17 May 2013 02:37:54 GMT

hi,dsp algorithm experts!

Almost everyone would say "using edma!" when I mentioned dsp algorithm optimization.

Many papers also said that edma played an improtant role in dsp algorithm optimization.

But according to my practices,edma played a good job in some condition and played a

bad job in another situation.In one word edma couldn't work well at any time.

Someone said using edma PING-PONG buf,but I couldn't see any change in performance

after I tried that method.

So I felt confused.Whether successful or failure case I couldn't know exactly why.

If EDMA worked well I couldn't know why.If EDMA worked badly I also couldn't know why.

I was dissapointed that I couldn't know the principle why edma improved performance.

Best Regards!

MCBSP of TMDSEVM6457L which used as SPI

yue zhang2 — Wed, 15 May 2013 12:09:15 GMT

I need to use the MCBSP configure as SPI to communicate with another SPI from ARM, but the examples of MCBSP from csl didn't use it as SPI so i sincerely hope anyone can afford me the code, the specific needs are as follows:
1. the mcbsp(spi) of TMSEVM6457L is the master which the spi from ARM is the slave
2, the data they transfor is 8-bits long
my email address is zhangyue198866@163.com

Error in dsplib (DSP62x.lib)

PAk SY — Sun, 21 Apr 2013 18:09:30 GMT

Hello all.

For an old 6202 device, I need to use the dsplib function DSP_fft16x16r, however the results I get are wrong. We are using "the same" function in an c6416 dsp (of course from dsp64x.lib), and in this platform we get the expected output.

We have tripled checked:

- the twiddle factors: we used the tw_fft16x16.exe file to generate those (const short w_16x16[2 * 510] ={......})

- the data align:#pragma DATA_ALIGN(w_16x16, 8);

- the call of the function:

DSP_fft16x16r(512, XX, w_16x16, brev, Y_16, 2, 0, 512);

Has anybody faced an issue like this? Does TI know about this issue?

Thank you.

Best Regards

Advisory 3.1.18 CPU: C64x+ CPU Incorrectly Generates False Exceptions for Multiple Writes

Ry38317 — Thu, 09 May 2013 17:10:10 GMT

We have a few questions regarding the silicon errata for the 6455 DSP. In particular We are looking at:

"Advisory 3.1.18 C64x+ CPU incorrectly generates false exceptions for multiple writes in the TI C6455"

SPRZ234Q.pdf page 35.

1) Towards the bottom of page 36 the document mentions that "The workaround also suppresses a particular valid exception..."
   From reading this, I'm under the impression that the stated workaround is only a PARTIAL workaround. There are cases in which we can't tell if
   the exception was from the silicon bug or an ACTUAL problem to worry about.

   We can't simply return to our runtime code if this is indeed an actual problem that was masked, how should we deal with this situation?

2) Given that we decide to use the detection mechanism described in the document and return to our runtime code, how can we force this errata
     problem and test our code upon returning with the NRP?

    Can we simply keep trying to get an interrupt to occur in the location as shown below, or are there more conditions that must be satisfied?

LDW *A0, A1
DOTP2 A3, A2, A1
NOP
-----------------> interrupt occurs
NOP
NOP ; Both LDW and DOTP2 write to A1 this cycle

3) Referring to document "TMS320C6000 DSP/BIOS 5.x" spru403r.pdf, towards the bottom of page 2-176 it states:

===
"In general, due to details of the ’C6000 architecture, NMI disrupts the
code it interrupts to the point that it cannot be returned to. Therefore,
NMI should not be used to respond to run-time events. NMI should
be used only for exceptional processing that does not return to the
code it interrupted.
"
===

This statement seems to conflict with the solution in question 2 where the errata states:

"Resume the interrupt handler by branching to NRP."

Please explain?

Trouble with callback about EDMA3

steve nice — Tue, 14 May 2013 09:17:01 GMT

hi,dear supports:

hardware:DM648

Recently ,I used EDMA3 LLD to transfer processed data from L1DSRAM to DDR or SDRAM.

My tese case used EDMA3 1D-copy to transfer image data.so Bcnt = 1,Ccnt =1 and

using AB-sync.Besides I used callback mode,every transfer was completed and callback

was called at the same time.

void callback (unsigned int tcc, EDMA3_RM_TccStatus status, void *appData)

{

EDMA3_DRV_Result result = EDMA3_DRV_SOK;

int *cbData = (int *)appData; unsigned short status2;

switch (status) {

case EDMA3_RM_XFER_COMPLETE:

*cbData = tcc;

trFinished++;

break;

case EDMA3_RM_E_CC_DMA_EVT_MISS:

evtMiss++;

break;

case EDMA3_RM_E_CC_QDMA_EVT_MISS:

break;

default:

break;

}

My app source code like this below:

for(i=0;i<count;i++)

{

DMA_CreateChannel(); //call EDMA3_DRV_requestChannel() and Set PaRAM set.

DMA_START(); //call EDMA3_DRV_enableTransfer();

DMA_WAIT(); //while(trFinished==0) ; before DMA_START trFinished = 0;

//after DMA completed ,callback was called and trFinished++

//so trFinished = 1;

}

But in my case,I meet a strange problem about callback.

when count = 8,there was nothing wrong with callback.everything was ok. Importantly,

when I debug register IPR and IPRH,I found corresponding bit was set As the tranfer was completed.

But,unfortunately when count = 352 (the number of count means the height of image data ,

every count DMA transfered one line),I meeet trouble.

Trouble 1:

when my code run at i = 14,the program was hung and entered into a endless

loop "while(trFinished==0);".Obviously,at i = 14,callback was not called so trFinished was

always 0.

so why callback was not called when i = 14?why callback was called when i = 0 to 13?

Trouble 2:

To solve Trouble 1,I debug my app code and I set breakpoint into callback.Although

callback was called from i=0 to i=13,the corresponding bit in reigster IPR and IPRH

was not set.

so,why not IPR and IPRH bit was set?

Best Regards!

MP Exception raised with reserved bit set in MPFSR

SPH — Tue, 14 May 2013 09:26:34 GMT

Hi,

One of the guys here has just experienced a memory protection fault where one of the reserved bits in the L2 MPFSR is set, despite the manual indicating that they should always read as zero.

The values that I am getting are L2MPFSR: 0x00000090, L2MPFAR: 0x00000000, which has bit 7 set in the MSFSR; the latest Megamodule Reference Guide states, in table 8-5, that this bit is read-only and always reads as zero.

What does this mean?

Thanks in advance,

SPH

why the clock() execution so time-consuming on EVM board

touse — Wed, 21 Mar 2012 02:27:15 GMT

Hi, all

I encounter a really strange problem. I want to profile our algorithm on EVM C6424, and when I use the clock() function for the profiler of several functions, the execution takes really a lot of time. But when I just read the TSCH and TSCL cycle counter instead of clock() function calls, the execution seems reasonable, about one tenth of the time consumed with clock() profilers. So can anyone explain to me why the time consumption differs so much?

By the way, I may call the clock() or read the TSCH, TSCL cycle counter 100 timers per frame, one frame corresponds to ~30ms playback.

Thanks for any reply.

Touse

EDMA3 error in TI datasheet!

steve nice — Sat, 11 May 2013 09:27:29 GMT

hi,ti experts:

Recently,I viewed the docment----sprue23d.And I found a error below.

the figure located on page 67 in sprue23d.pdf Data sorting example.

in the example.it used AB_sync.I thought SRCBIDX should be 0004h not 0001h.

Another,DSTCIDX should be 0004h not 0001h .Did you agree me?

TMS320C6455 downloader & test application

Il Heung Choi — Wed, 08 May 2013 07:22:16 GMT

(Please visit the site to view this file)

I am trying to implement a downloader; which is operating as the following.

1. burn the downloader to 0xB0000000 with emulator.

2. boot the DSP with EMIF 8-bit ROM mode.

3. download the application image via UART with XMODEM.

4. flash the received image to 0xB0020000.

5. jump to 0xB0020000.

It looks like operate with internal RAM.

However, H/W reset should be asserted after flash burning the received image. WHY???

Downloading and flash burning are successfully performed when the downloader use DDR.

However, it doesn't jump to the application even though H/W reset is asserted. WHY???

I am afraid you cannot understand my post because of poor English.

Please review my post and let me know the cause.

Thank you.

Regards,

Il Heung Choi.

Starting digital signal processing with TMS320C6713 DSP Starter Kit

Nikola Radakovic — Wed, 23 May 2012 21:46:02 GMT

Dear community,

Long time ago ( 2009 ) , I finished B.Sc. in computer engineering. I have a solid background in computer architectures, VHDL and analog interfacing. However, my professional background is mostly related to java and writing plugins for Eclipse. As I feel significant lack of knowledge concerning digital signal processing I bought a few good books dealing with DSP topics. The examples are written as a pseudo code. Since I learn much faster when I practically implement code , I would like to have a platform i.e. kit for practicing. Therefore, I would like to ask you a few questions regarding TMS320C6713 DSP Starter Kit ( hereinafter TMS Kit ).

1. Is TMS kit a good platform for a beginner to practice digital signal processing ?

2. I have noticed that DSK Code Composer Studio is included in Kit. The Kit costs around 400 USD, yet I have seen somewhere then some Composer Studio versions are around 20 000 USD ! Could you please tell me if Composer Studio coming with TMS Kit is adequate for ordinary beginner in DSP ?

3. Is it possible to run DSK Code Composer Studio under Ubuntu ( linux ) ? On screen shots, I have noticed that Composer Studio is written on top of Eclipse, hence mostly written in java.

I have also a professional version of Altium Desginer 10 but I don't possess signal generator nor oscilloscope, so I would like to have some platform for practicing digital signal processing. Any advice would be appreciated.

Many thanks,

Nikola Radakovic

EDMA Priority Queue Length

Aaron Hershberger — Mon, 06 May 2013 22:54:46 GMT

I noticed in an earlier post the ability to customize the three queue lengths within a particular priority with the limit that the sum must be =< 16.(SPRA994) My question is whether each queue type isn't limited to being =< 7. It looks like the register for setting the three types only uses three bits per type so values could range between 0-7 and you couldn't, for example, set the EDMA queue to 0, the TR queue to 1, and the L2/QDMA queue to 15.

I'm wanting to enqueue 8 QDMA requests at once so this appears to be my issue. This is all on a C64XX.

Thanks

C6455 --c64p_dma_l1d_workaround, are there any other options available?

Harish Natarahjan — Thu, 18 Apr 2013 13:58:50 GMT

We recently ran into an errata that discusses L1-D cache. A workaround proposed is to use a compiler directive (--c64p_dma_l1d_workaround). I also saw some subsequent errata for C674x that provides a bunch of different solutions. One of them is to allocate L1 as cache and all of L2 as SRAM (the default configuration which is how our DSPs are configured as well). Does this workaround also apply to C64X+?

The reason I ask is because I read notes stating that there might be some serious performance ramifications. If so, what are they and under what conditions would we experience it. In other words, is it better to stay away from this workaround if possible. Also, what is the eventual impact of this problem (I read one post that states that the issue will cause the DMA to be non-functional)?

Assuming that the only workaround available for C64X+ is the compiler option, would we still run into issues if there are libraries (for instance, libraries from third-party) are not compiled with the option turned on. What about the runtime libraries that TI itself provides. Are they created with this option turned on beginning with the tools version that supports this workaround or is that up to us to insure that? My tendency is to believe that we will minimize the probability of occurrence but not eradicate it (in the context of not turning on the option in libraries). What are our options in this scenario?

Your expedited answer to this question would be very much appreciated.

Is TCP2 in C6457 two bit complement

Daniele Ferramola — Thu, 02 May 2013 13:03:01 GMT

According to the TCP2 user guide for the C6457 DSP (SPRUGK1) p.13, it says symbols (data) have to quantized on 6 bits as (4,2) bit numbers => SIII.FF.

I want to identify that is it base on 2's complement or sign-magnitude??

For example, after quantized

-4 in 2's compliment : 0x11100

-4 in sign-magnitude : 0x10100

Which one is correct??

Thank you!!

Low cost DSP with a VCP

Reinier Coetzer — Tue, 30 Apr 2013 09:50:10 GMT

Good day experts,

I am looking for a TI DSP (preferably in the C6000 family) that is relatively low-cost but that has a Viterbi Co-Processor (VCP) peripheral. I can't seem to find a nice tool or something on TI's website to compare different DSPs with each other. We are currently using the C6418, but we would like to use a newer generation DSP.

Your help would be greatly appreciated!

Kind regards

Reinier

EDMA_MK_OPT argument order

Jonathan Mulvaine — Thu, 02 May 2013 13:02:51 GMT

Below is a copy and paste from C6x API Ref Guide(401). I am inclined to believe the other code in my project and the workshop documentation. Why (is it ok) are these listed in reverse order in the ref guide?

4.7.19 EDMA_MK_OPT Makes a value suitable for the EDMA OPT parameter
Macro EDMA_MK_OPT(
fs,
link,
tcc,
tcint,
dum,
d2d,
sum,
s2d,
esize,
pri
)

This may be the source of the document I used

http://www.ee.ic.ac.uk/pcheung/teaching/ee3_Study_Project/C6x%20API%20Ref%20Guide(401).pdf

unexpected variable behavior

Chris Roed — Thu, 02 May 2013 20:56:27 GMT

Hello, I'm using CCS5 with TI compiler 7.3.4 on a C6478 LCDK board.

I'm writing the UART communication scheme, and I'm seeing some odd behavior. I'm using an enum type to receive a uart command.

//enum declaration

enum rxstate_type {READY, START_BYTE_RECEIVED,LEN1_RECEIVED, LENGTH_RECEIVED};
enum rxstate_type rxstate = READY;

//in UART ISR

switch(rxstate)
{
//waiting to RX start byte
case READY:
temp = UARTCharGetNonBlocking(SOC_UART_2_REGS);
if(temp == STARTBYTE)
{
rxstate = START_BYTE_RECEIVED;
}
break;

case START_BYTE_RECEIVED:

rxArray[rx_count++] = UARTCharGetNonBlocking(SOC_UART_2_REGS);
rxstate = LEN1_RECEIVED;

break;

case LEN1_RECEIVED:
rxArray[rx_count++] = (UARTCharGetNonBlocking(SOC_UART_2_REGS));
rx_len = rxArray[0] << 8;
rx_len = rx_len + (rxArray[1]&0xFF);
rxstate = LENGTH_RECEIVED;
break;

///etc etc etc

My rxstate variable starts out as "READY"

When I received the startbyte, it successfully changes to "START_BYTE_RECEIVED". However, in LEN1_RECEIVED case, the rxstate doesn't change to LEN1_RECEIVED.

I've set a breakpoint and stepped through the code, but rxstate doesn't change. Any help with this would be appreciated.

Thanks

EDMA3 channel controller config register for different devices

Vladimir Dashevsky — Thu, 25 Apr 2013 14:32:35 GMT

Hi all,

now I'm working on EDMA3 driver for linux. I would like to teach the driver to configure itself based of values reported by EDMA hardware in EDMA REVID and CCCFG registers. The problem I see is that 64x processors (642x, 645x, 647x) and also 66x processors have the same 'rule' to compute number of resources (channels, regions, event queues etc) based on CCCFG. However, c674x DSPs have the same CCCFG values as C6424 but different number of resources. And, most strange, C674x have the same REVID (0x40015300) as C642x so it makes it difficult to prepare workaroud for it, looking only to EDMA features reported.

I wonder, is it a 'feature' of C674x hardware or some documentation failure? Unfortunately I don't have any 674x EVM to check REVID and CCCFG registers there.

Also, what was TI' planned use for EDMA3 CCCFG if not to provide standard description of EDMA features among all the family?

How to change TMS320DM642 MAC address ?

Stephenier Joe — Fri, 26 Apr 2013 02:07:01 GMT

Hi!

I build a web server on TSM320DM642 system ,and I use TI's example demon .

Now,I can run the project successfully, I can open the webpage of DM642 on my PC explore, and also I can change the IP address of DM642,but I can't change the MAC

address of DM642.

TI's example demon gives dm642 a MAC address of 'D':'4':'A':'1':'Z':'1', and can I change the MAC address? If can , how to chage ?

thanks very much !!!

TMS320DM6437 question

Gheorghe Plasoianu — Mon, 29 Apr 2013 09:23:01 GMT

we are using TMS320DM6437 in an automotive application. In stand-by mode the power supply of TMS320DM6437 is being switched off (all 3.3V, 1.8V and 1.2V) while the MCU of the device is still supplied. Therefore, the TMS320DM6437 get power supply from the MCU through different GPIO which accidentally remain high. Please comment if this procedure is ok for TMS320DM6437? If not, could we switch only 1.8V and 1.2V off and keep 3.3V alive to avoid supplying it through the GPIO and ESD diodes?

Thanks for your support,

Gheorghe Plasoianu