Hi. I'm a student, member of Brazil-IP Network (for more information: http://www.brazilip.org.br/ ) and i am developing a DMA based on TMS320C620x/C670x DMA Controller. More specifically, TMS3206202B/C6203(B)/C6204/C6205 are the target.
We(my team, DMA Team) have doubts about DMA configuration by CPU. The materials we have researched don't explain this process.
We know that CPU comunnicates with DMA through peripheral bus wich have 32bits wide. Thus, CPU have to send one configuration per time: First PRICTL, after SECCTL, after SRC, and so on.
Our doubt are:
-How CPU indicates the DMA channel that it want to configure?
-How many cycles are needed to configure? My friend suggested 4 cycles per register: First PRICTL, after 4 cycles SECCTL, after 4 cycles SRC, and so on, is this right?
Our material is: SPRU577A
Thanks.
Pedro Lopes -How CPU indicates the DMA channel that it want to configure?
Table 2-5 of SPRU577 on page 2-32 (or 69 of PDF file) indicates a set of registers for each DMA channel. Each DMA channel as a PRICTL, SECCTL, SRC, DST and XFRCNT register.
DMA Channel 0 : PRICTL0, SECCTL0, SRC0, DST0, XFRCNT0DMA Channel 1 : PRICTL1, SECCTL1, SRC1, DST1, XFRCNT1DMA Channel 2 : PRICTL2, SECCTL2, SRC2, DST2, XFRCNT2DMA Channel 2 : PRICTL3, SECCTL3, SRC3, DST3, XFRCNT3
You need to reference the specific DSP device datasheet to determine the unique address for each of the above 20 registers. For example the TMS320C6202B datasheet has a section for peripheral registers and in Table 4, the addresses of the DMA registers are defined.
Pedro Lopes -How many cycles are needed to configure? My friend suggested 4 cycles per register: First PRICTL, after 4 cycles SECCTL, after 4 cycles SRC, and so on, is this right?
Table 3-1 of the TMS320C620x/C670x DSP Program & Data Memory Controller/DMA Controller Ref.Guide (SPRU577) indicates the number of cycles required to access peripheral registers, of which the DMA controller registers are a part of.For a single access, 5 cycles.
Brandon
And about synchronization,
When any action of the selected event is completed, STAT is cleared(Automated Event Clering).
In this case, to clear the STAT is necessary to set CLR? Or CLR is set when we want to clear STAT manually?
Only CPU set CLR?
ow the CPU TMSC6202B configures the DMA?I think in this way:The CPU sends the address of the register that in the DMA and a write request. After this the CPU sends the data to the PRICTL. This routine continues until all the register is set. Is this???Please help me...Thanks again!:*
Camila Nunes ow the CPU TMSC6202B configures the DMA?I think in this way:The CPU sends the address of the register that in the DMA and a write request. After this the CPU sends the data to the PRICTL. This routine continues until all the register is set. Is this???
ow the CPU TMSC6202B configures the DMA?I think in this way:The CPU sends the address of the register that in the DMA and a write request. After this the CPU sends the data to the PRICTL. This routine continues until all the register is set. Is this???
Section 2.3 of the TMS320C620x/C670x DSP DMA Controller Reference Guide (SPRU577) discusses the Register access protocol to setup a DMA transfer.
Pedro Lopes And about synchronization, When any action of the selected event is completed, STAT is cleared(Automated Event Clering). In this case, to clear the STAT is necessary to set CLR? Or CLR is set when we want to clear STAT manually? Only CPU set CLR?
Section 2.4.1 of the TMS320C620x/C670x DSP DMA Controller Reference Guide (SPRU577) discusses how to use the WSYNCSTAT, WSYNCCLR, RSYNCSTAT and RSYNCCLR bits. Writing zeros to these bits does not have any effect. Writing a 1 to the (R/W)SYNCSTAT has the effect of manually setting the synchronization event. To clear the (R/W)SYNCSTAT bit, you need to set the (R/W)SYNCCLR bit. The CPU would do this.