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Digital Signal Processors (DSP)
C6000 Single Core DSP
C64x Single Core DSP Forum
writing fixed point code for 64x+ processor
I am writing a navigation algorithm code for the 64x+ processor. I am making use of IQ math library functions.
I am converting the floating point code into fixed point one...
There is a large variation of values in the numbers to as large as 9.9 and small as ten power -15 to ten power -23.
How exactly to deal the lower value range in fixed point.
64x+ is a 32 bit processor.
So in what way do i represent the lower value of numbers?? Will the processor be able to deal with such a low calue?? of the order of ten power -23??
The processing speed for fixed-point numbers on fixed-point processors used to be considerably faster than for floating point numbers on floating-point processors. That gap has narrowed with TI's latest C674x and C66x fixed/float DSP cores that combine the instruction-cycle speed of fixed-point processors with the computation power of floating-point processors. You may want to consider using one of the C674x- or C66x-based DSPs instead of whichever fixed-point C64x+ DSP you are current considering.
Which C64x+ DSP are you currently considering?
As I mentioned in your thread Writing a fixed point code for the DSP 64x+ processor, there are numerical issues that must be considered when using fixed-point numbers. You can start by searching the TI Wiki Pages for "C6000 numerical issues" (no quotes) which will help you find the C6000 Optimization Workshop. There is a module in the Student Guide for that class which introduces you to the issues with quantization and scaling of numbers. These are issues that can be handled mechanically by the IQMath functions and variable types, and that will need to be handled logically by you with your knowledge of which numbers should be scaled up or down depending on their range.
If some coefficients will always be small, you can group them with different scaling before adding them into the final calculations. If some of the input numbers will be up to 9.9 and some will be down to 10 pwr -23, you will need to do some dynamic scaling similar to Automatic Gain Control. But specifics on these topics may be found in college textbooks, or you could try searching TI.com or the web for educational material.
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I have been working on the fixed point code and have become familiar with the constraints involved in fixed point processing.the 64x+ core is the one which comes as part of the beagle board (ARM+DSP core).
When i mentioned the numbers of the order 10^-23, i meant that i will have to increase the precision in order to represent it in the fixed format, that is, it may go upto Q40 and Q50 format..
But i am wondering if there are methods of optimising such numbers so that they could be handlled in the 32 bit processor(64x+), and i am going through the student guide which was suggested by you.
Maybe you can try the block floating-point and pseduo floating-point, you can google to learn more about these methods or just follow the student guide for C6000 optimization workshop.
Digital Signal Processing, ARM DSPs, Embedded System, Multi-core Programming
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