Hi,
we are currently struggling with an issue related to PCI autoinitialization using an external 24C1024 eeprom connected to the C6454. The C6454 is connected through an XIO2001 PCIe bridge to a Patsburg (Sandy bridge) chipset on the other end. What we observe is that when the eeprom is correctly programmed with a correct checksum according to SPRUE60 chapter 12.4, then autoinitalization works correctly, and the device appears on the PC side with our SubVEN + SubDID as intended and the Vendor+ Device is also correct as 0x104C / 0xB000. The bootmode used is 14 (for PCI boot).
Reading out the JTAG device registers, we see Mfg ID=0x0017,Part=0x008A, variant=0x0002, which according to the SPRZ234 table 3 corresponds to silicon revision 2.1. The PCI bus is clocked at 66 MHz.
Now, before the eeprom has been programmed, it normally contains all FF (or random data) which means that the checksum of the PCI autoinitialization data will be wrong, and the DSP will reread the eeprom contents 50 (!) times before loading the default PCI configuration into the PCI config space. In our application, CLKIN1=50 MHz, and according to SPRUEC6G this means that the I2C bus is clocked at CLKIN1/6600 = 7.57 kHz. At 50 retries, the default PCI configuration will not be loaded until close to 10 seconds has passed !!!
During those 10 seconds, any attempt to access the PCI config space over the PCI bus (during BIOS enumeration of PCI devices) will lock up the PCI bus causing the PC to hang indefinitely - i.e. beyond those 10 seconds. No BIOS will (or should) wait for 10 seconds before trying to enumerate PCI devices, thus this is a major problem for the PCI boot mode.
Again, according to SPRUEC6G, table 8, it seems the I2C clock was clocked at a more reasonable 113 kHz (at CLKIN=50 MHz) for silicon revision 1.1 when using bootmode 14, but that this was changed when making silicon revision 2.1.
What we would like to do is to detect a "default PCI config" during PC enumeration, and then download a small program to configure the eeprom with the correct values to be used for autoinitilization. This currently seems impossible, unless there is a way to increase the default speed of the I2C bus for PCI init (bootmode 14) or reduce the number of retries from 50 to something more reasonable, like 0, 1 or 2. So, to my questions:
How can we reduce the time before the default PCI configuration is loaded upon PCI eeprom checksum failure?
How can we avoid the PCI and the PCIe buses being hung when the DSP does not respond to config space accesses while the eeprom is being re-read by the builtin bootloader?
Thanks ,
Torbjorn