I have a question that disturbed me for severial days;
I use daughtercard to connect to a FPGA and I configure the EMIFA of CE3 in synchronous mode.I found that I can write data to the FPGA,
BUT I cannot read data from the FPGA .
I am sure I configure the CE5CFG register of EMIFA correctly and the control signal of the EMIFA is the same as the timing in the datasheet .
BUT when I configure the EMIFA in synchronous mode ,what I read is always 0xFFFFFFFF,it sames that what I read is not the data in the interface
of EMIFA.IF I configure the EMIFA of CE0 which momory is cpld in synchronous mode ,I can only read 0xFFFFFFFF in the memory of cpld.
THANK you in advance!
By what method have you confirmed that the writes to the FPGA on CE3 complete correctly? Does something change on a pin or register of the FPGA that can be confirmed outside of the DSP?
When you look at the FPGA's pins during the synchronous read on CE3, do the EMIFA control signals look like what you expect from the datasheet? I think the answer is yes, from what you have said above.
Do the data pins contain 0xFFFFFFFF during the read phase? Or do you see the correct data coming from the FPGA? If you have writes configured correctly, you are likely doing the reads correctly, so you will need to look at the FPGA's response to those signals to confirm whether the FPGA is operating correctly.
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Thank you for your reply!
I have build a test project in the FPGA to detect the data writen from DSP and I am sure that it is complete correctly.
AND I also build a test project in the FPGA to send data to the DSP and I'm sure the data in the emifa interface is not 0xFFFFFFFF and the FPGA is completely right. but no matter what I send to DSP , It is always 0xFFFFFFFF.It is like that when I configure the emifa to synchronous read ,no matter what the data is in the interface,it can be 0xFFFFFFFF .
This I also mention that the board can't work correctly of the 6455_default_package\default_package\csl_c6455\example\emifa.It runs unsuccessful though other examles of the 6455_default_package work correctly.
I have doubted that the the board of mine DSK6455 has something wrong with the EMIFA synchronous read.
I really don't know why!AND I think I have to give up if the board of DSK6455 is broken in EMIFA.
when you connect the emifa in syn mode with fifo of fpga,there is something strange u should be careful.
read the 6455 datasheet error data. there is something may be helpful to you.
I have made a 64 channel adc with 360k sample/s and then use fifo to read data form fpga in syn mode ,and all is ok.
Thank for your reply!I am so glad to hear what you said!
But I don't quite understand that you have mentioned "the 6455 datasheet error data".What is this?
If possible ,can you tell me what I should pay attention to configuring the EMIFA in syn mode?
I have read the 6455 datasheet error data and I find it's not such helpful to me because i have payed attention to it before.
Could you please pass your project to me to see if it's something wrong with my DSK6455?My email address is email@example.com .I really need your help
because It troubled me for more than half a mouth.
In most cases, the DSK board is not failing but some configuration or method of use needs to be changed.
The DSK6455 is delivered with CSL and Board Support Libraries that will have an example that shows use of the EMIF to access on-board features such as the CPLD and switches and LEDs. Please try one or more of these examples to verify that the hardware is okay.
Please search this forum for other threads that have discussed the use of the synchronous interface. I recall there being a problem with this configuration due to the design of the CPLD or the routing of pins to the external memory interface connectors. I may be confused with the DSK6713, but it would be worth your effort to look for some of those discussions.
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