My application uses EDMA to read data from McBSP0. It's working fine if I don't configure the PLLs (using the power-on defaults instead). However, if I configure the PLLs for the desired clock rates, I no longer get any interrupts for the EDMA event (System event 34 on IRQ 5).
In the failure case, the startup sequence goes as follows:
1. Application processor (external ARM MPU) initializes the C6424 pinmux registers, sets DDR timings, and powers on the HPI and DDR modules.
2. It then downloads the DSP application binary to DSP DDR via HPI, sets the DSPBOOTADDR register, and takes the DSP out of reset.
3. The DSP comes up and disables HWI interrupts, configures PLL1 for the desired clock rate (700MHz), and powers up the remaining peripheral modules (including McBSP0 and EDMA).
4. Finally, it restores interrupts via Hwi_restore() and calls BIOS_start() which configures the Hwis, tasks, etc.
I've inspected the CSR, IER, ISTP, EVTMASK1, and INTMUX1 registers, and they all seem enabled properly (and identical to the success case).
I suspect that either the McBSP0 or EDMA modules are getting wedged during the PLL1 change, but am unsure how to fix it. Anyone have any ideas?
Thanks in advance,
There is no reason I can think of why the normal order of bringing up the device should cause the EDMA to fail. So, I suspect something in the EDMA module is getting messed up for one reason or another and needs to be initialized properly.
When in the process above do you open and initialize the EDMA3 module? I assume it is between steps 3 and 4.
There are a lot of registers in the EDMA module, so it would be hard to dump them all in some meaningful way to post here. Instead, see if you can read the values in the following EDMA registers, including the ones with H when there are two 32-bit registers: EMR, ER, CER, EER, SER, IER, IPR, and the active and link PaRAM for the channels you are using. Which DMA channels are you using for the McBSP0 operations?
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I'm using channel 2 for McBSP0 TX and 3 for McBSP0 Rx. Here are the registers and PaRAMs:
EMR: 0x00000000 EMRH: 0x00000000 ER: 0x00000004 ERH: 0x00010000
CER: 0x00000000 CERH: 0x00000000 EER: 0x00000008 EERH: 0x00000000
SER: 0x00000000 SERH: 0x00000000 IER: 0x00300000 IERH: 0x00000000
IPR: 0x00000000 IPRH: 0x00000000
PaRAMEntry (McBSP0 TX):
PaRAMEntry (McBSP0 TX Ping):
PaRAMEntry (McBSP0 TX Pong):
PaRAMEntry (McBSP0 RX):
PaRAMEntry (McBSP0 RX Ping):
PaRAMEntry (McBSP0 RX Pong):
I've compared all this to the case where the interrupt fires, and the following are different:
EMR: 0x00000008 ER: 0x0000000C IPR: 0x00300000
Another interesting datapoint: setting PLL1_PLLM to 0x0A (for a clock rate of 275 MHz) works ok. Setting it to 0x0B (clock rate 300 MHz) fails.
Well, according to the C6424 data sheet, the min and max values for PLLM are 0x14 and 0x32, so my findings above are probably meaningless. However, the power-up default seems to be 0x13. The data sheet must be incorrect.
In any case, I've found that the max value 0x32 works if I have the dividers set to 2/6/12. This gives a CPU clock of 637 MHz. Getting close, but I really need the 700 MHz we're paying for.
Setting PLLM to 0x1B and dividers to 1/3/6 is what I want, but it doesn't work for me.
I would have expected EER to be 0x0000000C to enable both DMA channels 2 and 3, but it is 8 enabling only channel 3. ER is 4, showing that an event is sitting there waiting to be processed for channel 2.
It is unusual to have Tx using TCC=0x14 and 0x15, and also having Rx using TCC=0x14 and 0x15. That makes them indistinguishable from each other when they have completed.
Are the few lines at the end of your EDMA post showing what is set when it works or when it fails? If when it works (interrupt fires, meaning okay), then it is the result of extra EDMA activity after halting it. EMR should never be non-zero, or some channels are locked and will stay locked; both ER bits being set says that the events have fired but the EDMA processing for those has stopped. This may all be because of the EMR bits.
Do you get the problems whether you do a cold start from power-cycling or from a warm reset just hitting the reset pins?
Can you post the code you use for setting PLL1? I am not an expert there, but we will try to find someone to look at it.
This turned out to be a sort of wild goose chase. The reason I wasn't getting interrupts was because I was trying to do a AB synch dimension and apparently the C6424 can only handle a 1D xfer. I can't explain why I was getting some interrupts when the PLLs were at power-up defaults, but it's working reliably now.
I'm on to the next issue now (more of a McBSP problem I think), but I'll start a new thread for that.
This is not true. The C6424 has EDMA3 and it can to AB sync for a single event 2D transfer. It can also support 3D effective transfers using multiple events and the CCNT/CIDX fields.
If you want to continue this thread to discuss the 2D vs. 1D, we will be glad to continue on it with you.
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