Recently I'm using EDMA to transfer data within L2 SRAM,and I've got some statistics about the speed of my data transfer.
Now I want to evaluate how my program works,in other word,I want to compare my transfer speed using EDMA with the available access rate of SRAM.But in TI's mannual I can't find the information about the access rate of SRAM.
My another question is:will the system clock affect the speed of data transfer?and How?Will the system clock also affect or limit the performance of EDMA?
Now I'm using DSK6455 and my system clock is 1GHz. My transfer speed is about 400Mb/s(only move some data form L2 to L2),is it fast or very slow?
I really hope someone can give me a hand.Thank you very much.
All data that we have available for these questions on specific internal operation of the devices is published in the relevant documents. Please look in the datasheet and the Megamodule Reference Guide. For chip-level interconnect within the device, we show bus widths and clock speeds; for Megamodule-level interconnect we show bus widths but I do not see clock speeds.
We design the devices to deliver the best possible throughput for applications. If you are trying to benchmark the device using artificial code, your results will vary based on your skill. If you have an application that needs to transfer 400Mb/s from L2 to L2, then we need to talk about why and what your actual requirements are, rather than trying to help you write code to prove what the device can do.
Yes, the system clock will affect the speed of all data transfers and EDMA operation. Everything will be linear within the device for components that run off linear divisions of the system clock. Please see the clock architecture described in the datasheet and Megamodule RG.
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