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C6748 EDMA

Chris Roed
Intellectual 960 points
Other Parts Discussed in Thread: TVP5147

Hello, I'm trying to configure the EDMA module (for the first time) and running into some issues.  The end goal is to use a DRDY signal from an ADC to trigger the EDMA transfer

In order to get started, I decided to trigger the EDMA with a switch (S2 on the LCDK).  The switch is connected to GPIO2[4].  I configured the pin along with an ISR to toggle one of the LEDS, and I configured the EDMA transfer to just move one byte from a variable called dummy to a variable called dummy1.  

I set up the EDMA to work from GPIOB2 interrupts, which translates to Event 22.  I think I'm required to use paRAM set 22, but I'm not sure.

I run the initialization, and I can verify that I've set the paRAM22 correctly.  the EER register has event 22 enabled, and the IER has int22 enabled.

I hit the switch and see my LED toggle, then I pause the debugger and  my entire paRAM22 set has changed to 0x00000000, the interrupt pend for int22 is set, the secondary event register for event 22 is set. and the Event Miss register shows bit 22 set.  The data from dummy is never transferred to dummy1.

Can anyone offer any assistance?

  • 0
    TI__Guru* 84110 points

    Chris,

    Do 1, 2, and 3 independently to help learn how the EDMA3 works and to let you figure out why each one changed something:

    1. Change the OPT.STATIC bit to 1. What happens differently now when you run your test and observe everything?

    2. Change both the source and destination addresses to external DDR2 memory space at 0xC0000000, or to the On-Chip RAM at 0x80000000. Does the dummy1 variable change now? What if you only change source or only destination?

    3. Change the Local L2-based dummy/dummy1 source and destinations by adding 0x11000000 to them. I am not sure where this is explained in the datasheet, but if you find any different results, we can talk about it.

    We have some good training material on the TI Wiki Pages. You can search for "c6748 training" (no quotes) to find links to some of the archived and video training available there.

    In the Training section of TI.com, there is a training video set for the C6474. It may be for a different device, but the EDMA3/QDMA/IDMA Module may help you understand some of the features and options available within the EDMA3 module, which is very similar to the implementation in the C6748. You can find the complete video set here. This may not be much help if you have already viewed the training material from the Wiki.

    Please let us know how the testing goes. It will let us know how close any of my guesses were. If nothing is gained, then we might need more information.

    Regards,
    RandyP

  • 0 in reply to RandyP
    Intellectual 960 points

    Randy,

    By the end of the day I had read and reread the paRAM section of the technical manual, and I think I have a good handle on how to link the sets properly now.  As you suggested, I moved my dummy variables around in memory, and I found that my EDMA transfer doesn't work in L2RAM.  If I put both of the variables in either SHRAM or DDR2, the transfer works.  I tried every iteration of transfering to and from DDR2, SHRAM, and L2RAM, and I found that none of the transfers with L2RAM work for me.

    I'm a little surprised by this, the technical reference manual has examples that explicitly call out L2RAM as the destination and source.  Upon futher investigation, I realized that the examples in the technical reference are using the SHDSPL2RAM.  

    Thanks for pointing me in the right direction.

  • 0 in reply to Chris Roed
    TI__Guru* 84110 points

    Chris,

    The L2RAM accesses must use the address that starts with 0x1180xxxx and not 0x0080xxxx. The 0x0080xxxx address is only accessible to the DSP core itself. All other bus masters, including EDMA3 must use the Global L2RAM address that starts at 0x1180xxxx.

    Please try this global address range for your L2RAM accesses. This was the item #3 in my previous post. Does that let the L2RAM accesses work right?

    The Global range startiing at 0x1180xxxx is an alias for the same memory starting at 0x0080xxxx for DSP accesses.

    Regards,
    RandyP

  • 0 in reply to RandyP
    Expert 1120 points

    Dear Randy,

    I am trying to connected a camera (OV7692) to the C6748 LCDK board.

    I get a frame with good HSYNC, VSYNC and PIX_CLK in RAW mode so that FVID_exchange works continuously (to get there, I removed the buffer in U27 and put the TVP5147 in shutdown mode).

    But, the EDMA does not update the data while I am getting video frames (VPIFIsr is received correctly).

    The DIN0-DIN7 toggle continuously at 2.7v Peek to Peek.

    What can be the problem?

    There is good video via TVP5147 in BT656 mode (embedded sync). The TVP HSYNC and VSYNC lines are not connected to the c6748 so I could not test the TVP in RAW mode.

    Thanks,

    Avi Tal.

  • 0 in reply to Avi Tal
    TI__Guru* 84110 points
    Avi,

    Please re-post this as a new thread. This thread is marked as Answered so it will not get as much notice from the best people.

    In your new thread, please include the software library revisions you are using. Also, explain where the VPIFIsr is coming from (EDMA or VPIF?).

    Regards,
    RandyP