Master Abort occurs in the PCI communication C6455

Yosio,

Please explain more about your comment "I can both Maser Write / Read, but he was no longer possible to communicate Master Abort occurs when repeated several times."

Do you see correct data show up on the Slave after a Master Write and correct data show up on the Master after a Master Read?

How many times does the test have to be repeated before it fails? How much data has been transfered? How is the test structured (alternating reads/writes, or all reads or all writes or something else)?

What happens just before the Master Abort occurs?

Regards,
RandyP

RandyP

that the data Master has Read is correct is seen in the Memory Browser Master Window.
that the data has been Master Write is written correctly, are seen in the Memory Browser Address of Slave DSP.

Number of tests is unknown.
I began to fail after a successful four times writing.
Since then, still unsuccessful, turn the power.

Succeeded twice after the writing began to fail reading, I have failed then.
It has not been the structure of the test.
I always fail.

The size of the data has two patterns available.
Writing has been successful both.
Reading has been successful only (1).
(1)
    int acnt = 4;
    int bcnt = 256;
    int ccnt = 1;

(2)
    int acnt = 16;
    int bcnt = 3766;
    int ccnt = 1;

It had become an invalid value before the Master Abort occurs, it is confirmed in Memory Browser the contents of the Master Window.
Master DSP side
 PCIADDSUB_9 0xB0000000

 0x4000000000 00 00 00 B0 04 00 00 B0 08 00 00 B0 0C 00 00 B0 10 ~

Slave DSP side
 PCIBARMIR_0 0xB0000008
 PCIBAR0TRL 0x00800000
 PCIBAR0MSK 0xFF800008

 0x0080000000 F7 31 27 06 F6 22 3C 02 12 14 1F 10 13 74 02 10 E4 ~

Or no possibility of the processing of PCI is not completed properly.
Completion detection is doing this.

regionIntr.region = CSL_EDMA3_REGION_1;
regionIntr.intr = 0x0; / / Often this is just a single bit
regionIntr.intrh = 0x0; / / high-bits if you are using them

/ * Poll IPR bit * /
do
{
    CSL_edma3GetHwStatus (hMoudle, CSL_EDMA3_QUERY_INTRPEND, & regionIntr);
}
while (! (regionIntr.intr & 0x1));

End processing is doing this.

CSL_edma3HwControl (hMoudle, CSL_EDMA3_CMD_INTRPEND_CLEAR, & regionIntr);
CSL_edma3ChannelClose (hChannel);
CSL_edma3Close (hMoudle);

I want you to tell me if you know something.
I want to say if there is information you need elsewhere.

Best regards.

Yosio,

This is excellent news. If you would, please post what the change was made to the PCICSR or what you observed that resolved the issue. This will greatly help the next users who encounter this problem.

Regards,
RandyP

I have already written.
I had to modify the value of PCICSR.
To put it more specifically, to change the value of Bit1 MEM_SP of PCICSR.
Slave's side.

I wonder can see in this.
I want to hear the place you do not know.

Hi Yosio,

We are also using two TMS320C6455 DSP's in our custom boards and PCI is the interface between the two DSP's.
Since we are new to the DSP and we are unable to get the PCI software in CSL for TMS320C6455, it will be appreciated if can share the changes needs to be done to configure DSP as master and Slave.

Thanks,

With Regards,
Mithun