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c6455 memory map problem

Surajkumar Mokhasi
Prodigy 200 points

Hi,

I have tried running the code by disabling the Cache (L1P_CACHE & L1D_CACHE) in gel file as follows.

*(int *)L1PCFG = 0;
*(int *)L1PCC = 0;

*(int *)L1DFG = 0;
*(int *)L1DCC = 0;

But still code execution is unpredictable.

When Data & Code is mapped to L2 SRAM . code is working fine.

Kindly suggest us what to be done for mapping the same to L1PRAM & L1DRAM correctly.

Note: If variable x is mapped to L2 memory (add: 0x00800008) has been verified using map file. But when we browse the same variable in memory browser the address appears to be 0x00000000. (Seems to be some linking issue). Kindly suggest on this also.

Regards,
Surajkumar

  • 0
    TI__Guru*** 125430 points

    I don't believe it's possible to use CCS to load code directly into the L1P SRAM.  The CPU has no way to write into the L1P SRAM and so generally you have to use DMA to relocate code to L1P at runtime as discussed in this article:

    http://processors.wiki.ti.com/index.php/Putting_code_in_L1PSRAM

  • 0
    TI__Mastermind 35645 points

    Hi Surajkumar,

    Thanks for your post.

    In my understanding, L1P by default is cacheable and you don't have control to disable the cache on the same. Even if you forcefully disable the cache on L1P, it will over ride and you will not see the effect on it. This leads to undesired code execution and you will not see desired output as expected. For your information, L2 P & L2 D shall be controlled in the gel file.

    Thanks & regards,

    Sivaraj K

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