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Please help connect DM6437EVM to CMOS MT9V032

Dear employee!

I want to do for the daughter board with sensor EVMDM6437 APTINA MT9V032.
I'm not sure how to connect these findings to the DM6437 
SYSCLK (Master Clock)
PIXCLK
LINE VALID
FRAME VALID

Thank you!

  • Hi Akchurin,

    I hope you’re using parallel way to interface image sensor module to DM6437,you need to use external crystal oscillator to generate 26.7MHz clock for SYSCLK input and connect the PIXCLK to VPBECLK on DM6737 device followed by

    Line Valid to HYSNC pin - An HSYNC indicates that one line of the frame is transmitted

    Frame Valid to – VSYNC pin - This signal is often a way to indicate that one entire frame is transmitted.

    Please refer the Aptina MT9D131 headboard schematics for more details

    7411.MT9D131_DemoHeadboard_C (1).pdf

    Regards

    Antony

     --------------------------------------------------------------------------------------------------
    Please click the Verify Answer button on this post if it answers your question.

  • Hi Antony!
    I have carefully examined the documentation and I had the two questions the answer to which will give me the correct wiring diagram.

    Can I not use the generator 26.7 MHz for SYSCLK CMOS. And use PCLK DM6437 connect to SYSCLK. This right?
    How to get CMOS SYSCLK of DM6437?

    MT9V032    --     DM6437EVM

    SYSCLK           <-- CLKOUT0 (Is that correct?)

    PIXCLK             -->VPBECLK (Is that correct?)

    LINE VALID       <--HS
    FRAME VALID  <--VS

    Dout0                -->CCD0
    Dout1                -->CCD1
    Dout2                -->CCD2
    Dout3                -->CCD3
    Dout4                -->CCD4
    Dout5                -->CCD5
    Dout6                -->CCD6
    Dout7                -->CCD7
    Dout8                -->CCD8
    Dout9                -->CCD9

  • Hi Akchurin,

    Please let us know which interface mode you are using to interface the CCD module, just be curious how you can connect the (DM6437) PCLK signal to (MT9V032) SYSCLK ,both are inputs by nature

    • Generic Parallel Interface – Raw CCD Data
    • ITU-R BT.656 Interface
    • Digital YUV Interface

     Please go through the VPFE - Video processing front end used guide for more details on how to interface the CCD module.

    http://www.ti.com/lit/ug/spru977d/spru977d.pdf

    Regards

    Antony

     

  • Hi, Antony!

    10-bit parallel from CMOS camera - RGB Bayer
    Parallel Generic Configuration (Raw) Signal Interface
    ====================================
    (DM6437) VPBECLK to (MT9V032) PIXCLK
    (DM6437) CLKOUT0 to (MT9V032) 
    SYSCLK

    (DM6437) HS to  (MT9V032) LINE VALID
    (DM6437) VS to  (MT9V032) FRAME VALID

    (DM6437)CCD0 to (MT9V032)Dout0                
    (DM6437)CCD1 to (MT9V032)Dout1                
    (DM6437)CCD2 to (MT9V032)Dout2                
    (DM6437)CCD3 to (MT9V032)Dout3                
    (DM6437)CCD4 to (MT9V032)Dout4                
    (DM6437)CCD5 to (MT9V032)Dout5                
    (DM6437)CCD6 to (MT9V032)Dout6                
    (DM6437)CCD7 to (MT9V032)Dout7                
    (DM6437)CCD8 to (MT9V032)Dout8                
    (DM6437)CCD9 to (MT9V032)Dout9
    ===================================           
    Please tell me this is the right configuration?


    (DM6437) PCLK not connected  (MT9V032) SYSCLK

    Do I understand correctly that (DM6437)PCLK is not used?

    CLKOUT0 - 27 Mhz for master clock to MT9V032

  • Akchurin,

    You need to use PCLK to connect to the MT9V032 PIXCLK

    Please refer the SPRU977D (Video processing front end guide) Page no 34 for Generic parallel interface –Raw CCD data and CCD interface signals for more details.

    CLKOUT can be connected to the  MT9V032 as a SYSCLK input.

    Use PCLK Instead of VPBECLK to connect to the MT9V032 PIXCLK ,please see the below tabel for more detials

    Regards

    Antony

     

  • Thank you for tech support!