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TMS320C6414T: HPI stops working while DSP operates normally

Other Parts Discussed in Thread: TMS320C6414T

Some boards of a board type with the TMS320C6414T show the error as described.

After powerup the DSP is booted by the host via the HPI (HPI32). After some successful HPI accesses /HRDY does not go active on a HPID Read from the internal RAM of the DSP. The access is terminated by the host after a timeout (60us). When the HPID Read is repeated, the result is the same (/HRDY not going active, bus timeout).

While the HPI is not working any more, the DSP continues to work normally (as seen from GPIO pins and from an emulator).

The only way to recover from this state is to reset and reboot the DSP. After a reset and reboot the error does not occur any more. i.e. the DSP enters the error state only after the first boot after powerup. This is a potential workaround.

The error occurs sometimes on some boards, never on other boards.

HPIA accesses in the error state:

In the error state the HPIA can be read from the host, it contains the last written value, unincremented. Reading HPIAW und HPIAR from the emulator returns the same result.

It is not possible to modify HPIA from the host. A write to HPIA from the host terminates normally, but the value in the register, as seen from the host and from the emulator, is unchanged.

It is possible to modify HPIAW and HPIAR from the emulator. Depending on the last HPID access, a read from HPIA by the host returns either the value in HPIAW or the value in HPIAR.

HPID Writes in the error state:

Writes to HPID terminate normally, but do not work. As seen from the emulator nothing is written to memory.

HPID Reads in the error state:

As already stated above the DSP does not go ready on HPID Reads, the access is terminated by a host bus timeout.

On the board the I/O supply ramps up before the core supply. Pin W25 is connected to Vss. We modified 2 boards so that the core supply ramps up before the I/O supply. With that modification on one board the error did not occur any more, on the other board the error still occurs.

Devices:

The devices are assumed to be

TMS320C6414TBCLZ7

 

Device Marking (see also attached photo):

TMS320C6414TCLZ

$N20-35ZC1S9

(c)2003 TI  82

            G1

            --

 

The device marking does not fully match the marking as described in the errata sheet ("$N20" instead of "D20"), but we assume that the devices are silicon revision 2.0.

The value read from DEVICE_REV (0x01b00200) is 0x00126414, that confirms that the devices are silicon revision 2.0.

 

Used documentation:

Data sheet SPRS226M - NOVEMBER 2003 - REVISED APRIL 2009

Errata sheet SPRZ216J, December 2003, Revised July 2012

Host Port Interface (HPI) Reference Guide SPRU578C, January 2006

 

Emulator and software used with emulator:

Spectrum Digital XDS510 USB

SDConfigEx Version 1.43.04

Code Composer Studio Version 4.4.82.13

 

Is there an explanation for the error state of the HPI?

Is there a way to recover from the HPI error state other than a reset?

Can we assume that the mentioned potential workaround is reliable?

  • Hello,

    On the board the I/O supply ramps up before the core supply. Pin W25 is connected to Vss. We modified 2 boards so that the core supply ramps up before the I/O supply. With that modification on one board the error did not occur any more, on the other board the error still occurs.

    You may see lot of issues in the device operation if you ramps up I/o supply before the core supply and this might be a reason for getting error on HPI.

    As per datasheet recommendation, the pin W25 should be left unconnected and not to be connected to power or ground. Why this pin is connectd to Vss in your design ? 

     

    Regards,

    Senthil

     

  • Hi,

    thanks for your response.

    Pin W25:
    According to the data sheet: Internal pull down, leave unconnected, do not connect to power or ground.

    But there is more information in the mentioned errata sheet:
    Usage Notes:
    Power Sequencing - IO Before Core
    If customers are using IO before Core, which was initially supported, it is required to connect the Reserved pin W25 to ground due to insufficient pulldown strength. If IO comes up before Core, and W25 is not at ground level, this can result in the device coming up in an improper state. To ensure this does not occur, it is required to connect W25 to VSS. If this is not done, then the power sequencing must be changed to Core before IO to ensure the internal state is set properly.

    In the errata sheet there is also an
    Advisory 1.0.11 PCI/HPI: Data Corruption Can Occur When DVDD Powers Up Before CVDD
    but it is listed only for Silicon Revision 1.0, so we assume that it does not apply for our silicon revision 2.0 devices and that we can use DVDD power up before CVDD.

    And as stated above, modifying two boards to CVDD power up before DVDD improved the situation but did not fully eliminate the error.

    Regards,

  • Hello,

    Could you please point out which errata document you are referring into ?

    I don't see any of your comment in C6414 errata available in below link.

    http://www.ti.com/lit/er/sprz011t/sprz011t.pdf

    Regards,

    Senthil

  • Hi,

    my enquiry is not about the C6414, but about the C6414T.

    The errata sheet for the C6414T is
    Literature Number: SPRZ216J,
    http://www.ti.com/lit/pdf/sprz216

    Regards,

  • Hi Miemwj,

    On the board the I/O supply ramps up before the core supply. Pin W25 is connected to Vss. We modified 2 boards so that the core supply ramps up before the I/O supply. With that modification on one board the error did not occur any more, on the other board the error still occurs.

    And as stated above, modifying two boards to CVDD power up before DVDD improved the situation but did not fully eliminate the error.


    After errata workaround, still are you facing any problem on the same board ?

    Have you checked and confirmed by probing the CVDD and DVDD signals on working and non-working boards ?

  • Hi,

    After errata workaround, still are you facing any problem on the same board ?

    We modified two boards, after that one board did not show the error any more, the other still did.

    Have you checked and confirmed by probing the CVDD and DVDD signals on working and non-working boards ?

    We have not found any differences between boards showing the HPI hang-up and boards not showing the HPI hang-up.

    Regards,

  • Hello,

    If possible, could you try power up CVDD before DVDD in some other boards and check the HPI error ?

    This is just to understand that the HPI error is due to silicon issue or design issue.

    Regards,

    Senthil

  • Miemwj,

    - How does the power up looks like? Do you have some screenshot of the ramp up the voltage rails? Can you confirm the sequencing?
    - Are the voltage rails clean, stable and within the specification during the complete operation? You have to measure it as close as possible to the device.
    Power supply and decoupling are key in High speed system. The "High-Speed DSP Systems Design ref -SPRU889" document was released at the time of the C6414T and details guidelines in term of decoupling and power supply.
    Make sure to review your PCB and align with those guidelines when needed.

    Anthony

  • Hi,

    I do not fully understand what you mean by

    AnBer said:

    Can you confirm the sequencing?

    but the attached pdf contains measurements of the power supply sequencing, in the normal case and on a modified board, and of the DSP reset.

    Regards,

    C6414T-HPI1.pdf
  • FYI, an access to the memory range 0x4000 0000 – 0x4fff ffff will cause the HPI to hang in the manner you describe.  I've seen many cases where there's a bad pointer, etc. where an unintended access is occurring to this memory range.  There are a few ways you could test this:

    1. Simplify your code considerably so the CPU is "out of the way", i.e. have it setup the HPI and then do nothing while you run some kind of HPI stress test.  If you never see lockups in this scenario that will strengthen that it might be related to a bad access.
    2. You could try a data watchpoint on that address range to see if you can actually catch the CPU in the act.

    I'm not sure if this is your problem or not, though I've run into this issue a number of times.  I thought I'd give another possible explanation since all the investigation so far is geared toward the supply sequencing (which may very well be part of the issue).

  • Unfortunately this problem is still not solved...

    We are quite sure that neither the DSP nor the host access the forbidden memory. However, we found something rather awkward. If (before loading the DSP image to the DSP RAM and booting it) we connect to the DSP via a JTAG-debugger and immediatelly disconnect again, the problem does not occur. By "connect" I mean pressing the "Connect Target" button in CCSv5. Even more precisely, we figured out that it's probably not the connecting that fixes the problem, but rather the disconnecting. Because if we only connect and stay connected while the DSP is being loaded and bootet, HPI stalls again.

    We use an XDS510 USB debugger from Spectrum Digital, and Code Composer Studio Version: 5.3.0.00090. In the "Debug Configurations" we disabled all options that might change anything on the DSP after connecting.

    Do you know what exactly happens on the DSP when connecting to it via JTAG? Are there any registers or addresses automatically read or written?
  • I don't know all the details of what happens on a connect, but an easy thing to potentially look into first would be the TRSTn pin. I think this behavior varies by emulator, but at some point (either when plugged onto the header or when connecting) the TRSTn pin is de-asserted (high) in order to bring the jtag logic out of reset. Upon disconnecting (implementation dependent?) it would be brought back low. So that begs the question -- do you have TRSTn pulled low on your board? I've run into a number of cases over the years where TRSTn was pulled high or sometimes even picking up noise while floating causing weird startup issues.
  • I think we solved the problem finally. By accident we found this thread:

    http://e2e.ti.com/support/dsp/tms320c6000_high_performance_dsps/f/115/t/153708#pi239031349=6

    Quoting from there:

    This macro:

    VEC_ENTRY .macro addr
        STW   B0,*--B15
        MVKL  addr,B0
        MVKH  addr,B0
        B     B0
        LDW   *B15++,B0
        NOP   2
        NOP  
        NOP  
       .endm

    should not be used for the rest vector (it is ok to use it for other interrupt vectors).  This macro is apparently used due to some misleading TI reference documentation about how to form a reset vector when not using DSP/BIOS (my take from posts in this thread....   ).  

    The reset vector should contain:

        MVKL  addr,B0
        MVKH  addr,B0
        B     B0
        NOP
        NOP
        NOP
        NOP
        NOP

    where addr is the address you wish to jump to on a reset.

    Indeed it turned out that after a cold start the register B15 often contains a value of the forbidden address range 0x4000 0000 - 0x4fff ffff. However, it seems that the JTAG debugger modifies some of the registers, which is why we could never capture the illegal access.

    I'd like to point out that the incorrect code can still be found in the TI reference documentation (though, in our case that code has been in our software for many years...).

    Regards and thanks for support,

    Georg

  • Thanks for sharing. I remember spending a lot of time on that issue so I'm glad you were able to find it and solve your problem! That's great news.