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how to using cache with C6455

    hello,  I'm using cache on c6455, I stored image data on DDR2,and the data is transfered by edma3 in ISR, after that I process the image data in a task, here is the pseudo-code

  /*image data  stored in */

  Uint16 img_data[640*512];

/* process result*/

/*data receive interrupt*/

Uint8 process_result[120];

   void img_ISR(void) {

     BCAHCE_inv(img_data,sizeof(Uint16),0);

    edma3_tran(img_data,data_src,sizeof(Uint16));

     SEM_post(&sem_process);

   }

/*data process task*/

void process_tsk(void){

    while(1){

       SEM_pend(&sem_process,SYS_FOREVER);

       ....process image data

       ....

         BCAHCE_wb(process_result,120,0);  

         edma3_tran(dst_addr,process_result,120);

     }

}

 

 but when I check the image_data for example, I copy image data into another array(temp_array[640*512]) using CPU, I found the data is different between temp_array and image_data. I don't why this happen, does I did'nt  correctly maintain the cache coherence , can anyone tell me the reson, and give me an advice about using cache.

   thank you!

  • Hi,

    Thanks for your post.

    In general, there are three available cache memories in the C6455, L1P, L2D, and L2. These have a configuration at reset and they also have a configuration based on CSL or BIOS commands and the BIOS configuration or platform files.

    In addition, the Memory Attribute Registers (MAR) are used to enable cacheability on specific memory ranges.

    For better understanding on cache usage, cache characteristics and cache optimization, you could refer the C64x+ DSP cache user guide as below, please refer section 2.4.2.2 for maintaining coherence between external memory and cache and there is an example 2-4 for external memory DMA double buffering code, kindly check it

    http://www.ti.com/lit/ug/spru862b/spru862b.pdf

    Also, there is an example for cache coherence for DMA accesses to L2SRAM (DMA write/read to/of L2SRAM). Please refer section 2.4.2 and Example 2-3)

    Thanks & regards,

    Sivaraj K

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