TMS320C6418 problems with SDRAM

Hi Alexey,

Please take out the SDRAM timing parameters from new SDRAM data sheet and configure it.

First try to modify the gel file and confirm that SDRAM works good with latest configuration through CCS.

The below wiki for OMAPL138/C6748 but also you can refer for EMIF configuration.

http://processors.wiki.ti.com/index.php/Programming_Asynchronous_EMIF_on_OMAP-L13x_/_C674x_/_AM1x

>>Please take out the SDRAM timing parameters from new SDRAM data sheet and configure it.

The trick is, that both: new&old  SDRAM are covered by the same datasheet. No difference in timing, all the timing para meters are exactly the same. Both: D&E SDRAM revisions are covered by the same datasheet. 

http://www.micron.com/parts/dram/sdram/mt48lc16m16a2tg-7e      

Hi Alexey,

If both the SDRAM were same then what is the exact difference between them ?

Is there any parameters differed between 2 SDRAMs ?

The difference is the die shrink. 

Revision :D  was 130 nm  

New Revision :G is 54 nm  

Please go to http://www.micron.com/parts/dram/sdram/mt48lc16m16a2tg-7e

Choose Documentation and Support  tab and open document called: 

SDRAM I/O Characteristics Comparison of 54nm to 130nm Die: (PDF 515.31 KB)This technical note compares the I/O characteristics of the 54nm to the 130nm single data rate (SDR) synchronous dynamic random access memory (SDRAM) die.

Micron SDR SDRAM devices built with the 130nm process have been available and in

use for many years. However, it has become necessary to migrate these devices to a
smaller 54nm process to take advantage of the latest manufacturing processes and
technology.
The SDRAM devices built with the 54nm process are fully compatible with those built
with the 130nm process. However, there are differences in the I/O (driver and receiver)
characteristics between the 54nm and 130nm devices.

The problem is actually, that there are not too many SDRAM manufactureres world-wide left and Micron is the leading one with longevity programm on this. A lot of legacy designs on Ti DSP's are still produced on old SDRAM. And we would like to  understand the reason  of such memory failures.

Thanks for support.         

Hi Alexey,

Thanks for your detailed information.

From software point of view, I don't have any suggestions on this so I ask our hw experts to look into the problem.

Just to confirm, it is like drop and replacement ? or is any hw schematic has been changed for the new SDRAM ?

I presume that you are testing SDRAM with CCS through JTAG by modifying gel file.

Alexey,

[I am not the hw expert that he is referring to, but I wanted to join the discussion.]

What are the I/O differences? Do these affect timing in any way?

If the new revision is timing compatible with the old revision, then either the timing values that your customer has used were not correct for the old revision but happened to work (just lucky) or the I/O differences cause timing changes that are not accounted for. Or the new revision is not meeting their timing specification, but that would be unlikely.

What are the memory problems they are experiencing? Read failures, write failures, refresh/retention failures?

Who generated the timing register values for the old revision? Was this done by the customer or copied from an existing EVM or reference design from TI? Or by you or your team?

The customer, or you, will want to go through every timing parameter and make sure that the old settings were correct. Make sure the +1 or -1 is comprehended for any values that have that confusion (for value N, program register with N-1, for example). I am not in a position to do this evaluation for them.

If everything looks right, then they will need to debug the problem by looking at waveforms to make sure timing looks right, or does not look right. They can vary timing parameters by +1 or -1 to see if changing any parameter fixes the memory problem.

Are you or your customer able to do these things?

Regards,
RandyP

hi, any news or update about this issue with sdram?, Did you solve this problem?

Hi Alexey/Mariano,

Have you contacted MICRON team for this issue ?