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ACPY3 queue full and cpu stall behavior

Dehuan Xin94
Intellectual 520 points

Hi, guys,

I see in this wiki page:

http://processors.wiki.ti.com/index.php/Framework_Components_DMAN3/ACPY3_Users_Guide#DMA_Transfer_Submission_and_Synchronization_using_ACPY3

In order to start multiple DMA transfers simultaneously but in a strict FIFO order, the IDMA3 interface introduces the notion of logical channels with more than 1 configurable transfer.

Does this means that, after starting one transfer on a logical channel, one can immediately reconfig that channel
and start it again?

What's the queue length, or, the upper limit of pending transfers?

In the worst case scenario, if the queue is full, is it going to cause cpu to stall or a transfer miss?

Thank you.

Dehuan

  • 0
    Intellectual 520 points

    OK, in the same page:

    ACPY3_start returns to the caller (the algorithm) as soon as the transfer request is submitted to a logical or physical hardware queue or devices that will asynchronously perform the copy operation.

    Effectively, the answer to the first question is "yes" and to the last question is "stall"?

  • 0 in reply to Dehuan Xin94
    TI__Mastermind 35645 points

    Hi,

    Thanks for your update.

    Yes, you are right, the CPU should stall untill the queue is emptied and will wait for the packets to complete transfer if the queue is full.

    Thanks & regards,

    Sivaraj K

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  • 0 in reply to Sivaraj Kuppuraj
    Intellectual 520 points

    Hi, Sivaraj,

    Is this queue length the hardware queue length or a software layer queue length?

    Is there a documentation about the length of it?


    Dehuan

  • 0 in reply to Dehuan Xin94
    TI__Mastermind 35645 points

    Hi,

    Probably, it should be a software layer queue length and i don't think, we could find collaterals for the same since it is software based queue configuration.

    Thanks & regards,

    Sivaraj K

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