Hello,
In my project there are two dsp's communicating with each other on bases of GPIO interrupt via a FPGA throuhg EMIF interface.
EMIF has synchronous configuration
1. Chip Enable register Values for DSPx - CE2 -> 0x8000000E
2. Chip Enable register Values for DSPy -CE5 -> 0x8000000E
I set MAR bits(160 bit) for DSPx and MAR (208 bi)t for DSPy to configure external memory as cache because of that DSPy is not able to receive GPIO interrupt from DSPx.
Except MAR register is there any other register has to be set to configure external memory as cache.
Thanks,
sanjay