C6457 Cache enable problem

user4171244

Hello,

In my project there are two dsp's communicating with each other on bases of GPIO interrupt via a FPGA throuhg EMIF interface.

EMIF has synchronous configuration

1. Chip Enable register Values for DSPx - CE2 -> 0x8000000E

2. Chip Enable register Values for DSPy -CE5 -> 0x8000000E

I set MAR bits(160 bit) for DSPx and MAR (208 bi)t for DSPy to configure external memory as cache because of that DSPy is not able to receive GPIO interrupt from DSPx.

Except MAR register is there any other register has to be set to configure external memory as cache.

Thanks,

sanjay

over 9 years ago

0 Titusrathinaraj Stalin over 9 years ago

TI__Guru** 116100 points

Hi Sanjay,

Could you please tell me that how did you know and change the MAR 160 and 208 bit to configure the ext memory as cache ?

Which document are you referred ?

Please note that configuring ext memory as cache, it could lead to errors (coherent etc.,)

No other registers are available to configure the memory as cache.

Like DSP mega module and DSP memory user guide doc etc.,

Please refer to the following TI wiki.

http://processors.wiki.ti.com/index.php/C6457_Improvements_Over_C6455

http://processors.wiki.ti.com/index.php/Enabling_64x%2B_Cache

http://processors.wiki.ti.com/index.php/Cache_Management

http://processors.wiki.ti.com/index.php/Common_Issue_Resulting_in_Slow_External_Memory_Performance

0 RandyP over 9 years ago

TI__Guru* 84110 points

Sanjay,

You are not setting the external memory as 'cache' but as 'cacheable'. The only cache memory is inside the DSP, if you have configured any of the internal memory as cache. The default is for all of L1D to be cache memory and all of the L2 to be SRAM.

Your external memory locations addressed by the CE2 and CE5 address ranges will appear to be memory locations to the DSP. If you set the MAR bit, then those locations will be cached internally by the DSP.

This is not a good thing to do for most uses of an FPGA, especially when it is implementing memory-mapped I/O or dual-port memory. Make sure MAR160 and MAR208 are left at 0 so those memory ranges are not cacheable.

You can check the MegaModule Reference Guide to see the other cache related registers, such as L1DCFG.

Regards,
RandyP

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C6457 Cache enable problem