Just checking that if I use some L2 cache as SRAM, it is only cached by the L1D cache.
This matters when I align the data for DMA, with the cache coherency games, I could align everything to L2 cache line size and thus do the cache flush/clear at the larger size and be safe.
However some of the objects are small and I want to pack them tightly with the minimum appropriate cache line size.
Silly question I hope, but perhaps forestalling something really hard to debug.
Targets are 6412 and 6415.
Chris