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Cache architecture confirmation

Just checking that if I use some L2 cache as SRAM, it is only cached by the L1D cache.

This matters when I align the data for DMA, with the cache coherency games, I could align everything to L2 cache line size and thus do the cache flush/clear at the larger size and be safe.

However some of the objects are small and I want to pack them tightly with the minimum appropriate cache line size.

Silly question I hope, but perhaps forestalling something really hard to debug.

Targets are 6412 and 6415.

Chris

  • Hi Chris,

    Could you please elaborate a bit on your question.

  • Hi,

    Thanks for your post.

    I think, it would be better recommended for you to check for the c6474 training video set which uses three of the C64x+ cores. It may be helpful for you to  review several of the modules. But in particular, the Memory and Cache Module  will apply to handling the cache coherency issues. You can find the complete  video set at

    http://software-dl.ti.com/public/c6474/C64x_Memory_Cache/index.html

    Thanks & regards,

    Sivaraj K

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  • HI,

    If the cached address falls in the L2SRAM, then you are feasible to use and this will be decided by the CPU through the cache configration which the user had set. Usually, the CPU will check the cached address falls in which level of cache memory controller but the DDR cache controller will read the whole cache line and will be saved in L2 Cache memory and will be forwarded to L1 program cache memory & will be saved to it. Then a fetch packet will be sent to CPU and accordingly, it will execute the code.

    i guess, if your address range is not properly cached, then it would be a cache miss and also, you need to understand the cache coherency issues accross different levels of cache controller.

    Thanks & regards,

    Sivaraj K

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  • Chris Thomas said:
    Just checking that if I use some L2 cache as SRAM, it is only cached by the L1D cache.

    Chris,

    This statement is correct. Data stored in L2 SRAM will not be cached in other L2 cache but only in L1D cache.

    Regards,
    RandyP