Here are my steps:
1. Host uploaded DSP code via HPI and then Host asserted HPI DINT bit to wake DSP up. This part is working fine.
2. After DSP woke up and ran its code, DSP code acknowledged HPI DINT bit by writing 0x00000002 to the HPIC register.
3. Then DSP wrote some "ready" message to L1D SRAM at location 0x00F00400, and asserted HINT bit by writing 0x00000004 to the HPIC register.
4. Upon receiving HPI interrupt from DSP, Host read the message via HPI interface, but I read garbage data.
If I added delay (~ 1000 ticks) in between step 2 and 3, Host could read correct message via HPI interface. However this is not a desired solution without knowing for sure how long it takes for the HPI interface to be ready.
I checked both internal HRDY bit as well as HRDY_N pin, and both indicated HPI ready right away after DSP woke up.
So, what is the minimum wait time Host to wait after DSP code woke up before it could access DSP memory via HPI?
Thank you.