C6454 EDMA transfer controller hang on read

James Zhang

I am using EDMA on DSP:c6454.

EDMA setup:

        OPT     unsigned int            0x8001B004 (Hex)              
        SRC     unsigned int            0xE270098E (Hex)              
        A_B_CNT unsigned int            0x000D0002 (Hex)             
        DST     unsigned int            0xB0200E00 (Hex)              
        SRC_DST_BIDX    unsigned int    0x00000002 (Hex)              
        LINK_BCNTRLD    unsigned int    0x0004FFFF (Hex)              
        SRC_DST_CIDX    unsigned int    0x00000000 (Hex)             
        CCNT    unsigned int            0x00000001 (Hex)             


The transfer controller hang on read with the following register values:

EDMA3TC0_SAOPT
0001B010
EDMA3TC0_SASRC
E270098E
EDMA3TC0_SACNT
0000001A                              <----- Acnt = 2*0xD = 0x1A, but why BCNT=0?
EDMA3TC0_SADST
00000000
EDMA3TC0_SABIDX
00000002
EDMA3TC0_SAMPPRXY
00000100
EDMA3TC0_SACNTRLD


I understand the transfer controller optimized from a 2D-transfer to a 1D-transfer, that is why the SACNT = 2*0xD = 0x1A
but why the Bcnt = 0?, should it be 1?,  is that the reason the read hang?

Thanks

James

over 9 years ago

0 Sivaraj Kuppuraj over 9 years ago

TI__Mastermind 35645 points

Hi James,

Thanks for your post.

Yes, you are right. BCNT should not be 0. For normal operation, valid values for BCNT are between 1 and 65 535 and a transfer with BCNT equal to 0 is considered either a null or dummy transfer.

For more info. on BCNT, please refer section 2.3.2.5 in the C645x EDMA3 user guide as below:

http://www.ti.com/lit/ug/spru966c/spru966c.pdf

For details on dummy/null completion conditions, please refer sections 2.3.5 & 2.5.3 from the above user guide.

Thanks & regards,

Sivaraj K

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0 James Zhang over 9 years ago in reply to Sivaraj Kuppuraj

Prodigy 170 points

Hi Sivaraj

The bcnt in my setup in the PARAM is not 0, it is 2. The transfer controller recalculated the bcnt or did something to it, and the bcnt changed to 0 in the transfer controller Source Active Count Register.

I don't know why transfer controller recalculate it. did the transfer controller try to optimize the transfer by changing the 2-D transfer to 1-D transfer?

My source address is not even the power of 2. According to EDMA guide, the transfer controller should not even optimize it. So something is wrong in the transfer controller?

Thanks

James

0 RandyP over 9 years ago in reply to James Zhang

TI__Guru* 84110 points

James,

Are your transfers occurring correctly? Are all of the 26 bytes from the source transferred to the correct locations starting at the destination address?

You are looking at internal debug registers that are not generally examined under normal operation. Fully understanding the bit fields and the operation of the Channel Controller to generate the Transfer Request would require more detail on the device than I have access to and much more than we document in the EDMA3 User Guide.

In cases where your transfers are not operating correctly, we can often use these registers to help us understand what problem you may be having. But if your transfers are behaving correctly, we will have to all accept that these registers are not fully documented and that some parts of the optimization algorithm are not limited the way you expect them to be limited.

It is commendable that you are looking this closely at the internal registers and trying to understand more detail. I am sorry we do not have more documentation to offer, but I am hopeful that your transfers are behaving correctly.

Regards,
RandyP

0 James Zhang over 9 years ago in reply to RandyP

Prodigy 170 points

Yes, I just found out that the transfer did finished correctly.

Thanks

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C6454 EDMA transfer controller hang on read