This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

C6455 sysclock test

Hi all,

I designed one target board with C6455 DSP. But i encounter XDS560 emulator connecting error.

The log is :

Error connecting to the target:
Error 0x80000240/-233
Fatal Error during: Initialization, OCS,
This error was generated by TI's USCIF driver.

SC_ERR_PTH_BROKEN <-233>
An attempt to scan the JTAG scan-path has failed.
The target's JTAG scan-path appears to be broken
with a stuck-at-ones or stuck-at-zero fault.
 
I have tested the power, PLL1 50Mhz /PLL2 25Mhz, is good. The POR and RESET is tied together to reset circuit.
AEA4(SYSCLKOUT_EN) is pulled high, then i test SYSCLK4/GP[1] pin. There is no clock output.
Does my DSP not workup?  And my SYSCLK test method is right??
 
Thanks!!
 
  • Hello Guochao,

    Welcome to the TI E2E forum. I hope you will find many good answers here and in the TI.com documents and in the TI Wiki Pages (for processor issues). Be sure to search those for helpful information and to browse for the questions others may have asked on similar topics (e2e.ti.com).

    Are you using custom board or TI EVM ?

    You cannot see any output at SYSCLK4/GP[1] pin unless you performed the PLL initialization.

    The possible reason for the above JTAG errors as follows.

    1. A broken signal path from JTAG header signals to the C6455. The most likely signals are TDO, TDI, and TCK, but any of the signals could be involved.
    2. Other primary control signals to the C6455 that could prevent it from operating at all. Check all power supplies at all C6455 power pins including grounds, check all clocks and resets, and check all configuration pins that should be pulled to the proper state during reset.

    Regards,
    Senthil