I am using C6455 DSP.
Currently I am setting up two DMA channels:
- Rx (Channel 55 on Queue 0). It gets triggered when GPI 7 gets asserted (EVT55) which happens every 11.5us. Per transaction DMA reads 1x28 bytes
- Tx (Channel 53 on Queue 1). DSP code initiates the transaction every 625us. In a single transaction DMA writes 54x8 bytes.
How do I set the DMA so that once the write transaction begins, it can not be interrupted by the other DMA transaction?
I saw on LA that sometimes DMA read transaction happened in the middle of the DMA write transaction, and it delayed the completion of DMA write transaction.
I thought Channel 53 DMA has higher priority than Channel 55 DMA, therefore I am expecting DMA hardware to finish writing the whole 54x8 byte before reading 1x28 byte if the read transaction occurs in the middle of write transaction.