POR for EMIFA(C6457)

pramod kashyap

Intellectual 615 points

Other Parts Discussed in Thread: TMS320C6457

Hello,

We are using DSP TMS320C6457 in our Design,

In our design POR for DSP is generated by FPGA,

Is POR required to generate EMIFA Core Clock(60 MHZ) ?

Thanks,

Pramod

over 8 years ago

0 Senthilkumar Srinivasan over 8 years ago

TI__Mastermind 43660 points

Hello Pramod,

Are you using external input clock (AECLKIN) or SYSCLK7 for EMIFA ?

If you are using SYSCLK7, POR is really required. Only then the RBL intiates the PLL controller and generates the SYSCLK7.

Regards,
Senthil

0 pramod kashyap over 8 years ago in reply to Senthilkumar Srinivasan

Intellectual 615 points

Hello,

In our design FPGA is giving POR to DSP,

But we have stopped Giving POR to DSP from FPGA,

But still we are getting 60 Mhz from AECLKOUT pin(EIMFA CLOCK),

Please revert back ASAP.

Thanks,

Pramod

0 Senthilkumar Srinivasan over 8 years ago in reply to pramod kashyap

TI__Mastermind 43660 points

Hello Pramod,

Could you please answer my question in the above post to analyze your query in a better way.

Regards,
Senthil

0 pramod kashyap over 8 years ago in reply to Senthilkumar Srinivasan

Intellectual 615 points

Hello,

We have tied AECLKIN to GND through 4.7Kohm resistor no external clock taken,

After Booting we are getting SYSCLK7 setting Clock,

If we don't Boot DSP what will be AECLKOUT Signal Status?

Thanks,

Pramod

0 Senthilkumar Srinivasan over 8 years ago in reply to pramod kashyap

TI__Mastermind 43660 points

Hello Pramod,

Thanks for answering the question.

When you are not booting the DSP i.e., not providing POR to the SoC, we may not predict the state of the internal logic. In your case, i think the PLL takes the earlier settings of PLLM and PLLD and gives the SYSCLK7 at AECLKOUT pin.

After power recycle, we recommend to provide POR to SoC for proper initialization of all the peripherals. If you are not, you may not expect proper device operation.

Regards,
Senthil

0 pramod kashyap over 8 years ago in reply to Senthilkumar Srinivasan

Intellectual 615 points

Hello,

Thanks Senthil,

I did'nt get by what is Earlier settings of PLLM and PLLD,

Is it Default settings?

Please can you elaborate me on that,

Thanks,

Pramod

0 Senthilkumar Srinivasan over 8 years ago in reply to pramod kashyap

TI__Mastermind 43660 points

Hello Pramod,

I meant to say the PLL takes the same PLLM and PLLD settings during PLL initialization which happened before you do power recycle.

Regards,
Senthil

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POR for EMIFA(C6457)