SPKERNEL (fstg, fcyc)

fstg, fcyc is very simple. Imagine for a moment that SPKERNEL didn't support extra argument (which would be equivalent of passing 0,0 at all times). You have to recognize that execute packet following one with SPKERNEL is scheduled for execution at ii*n-th cycle, where ii is argument to SPLOOP instruction and n is initial ILC value. But what if it's not the time to execute that instruction/packet at that point yet? In such case you'd have to add some NOPs to wait for right moment, right? And fstg,fcyc is nothing else but a way to express corresponding delay. But what are their values? Even simpler. If you have to postpone first instruction/packet following the loop by j cycles, then fstg is j/ii and fcyc is j%ii. That is all to it.

As for suggested example. It's not representative, because the loop body is as long as ii. And there is no reason to postpone instruction/packet following SPKERNEL, whichever absent. For this reason it's impossible to illustrate what fstg, fcyc are useful for. However, it should be noted that operation in question can be performed with SPLOOP 2, or [asymptotically] 6.5[!] times faster than suggested example. In such case you'd be likely to have to use fstg,fcyc. Indeed, imagine that the missing instruction was return from subroutine. Would you want it to start execution at 2*n-th cycle? No. Because at that point you'd still have 11 cycles to go till the last instruction of the last iteration of the loop body. But return from subroutine gives you only 5 extra cycles, after which execution control is passed to caller. And passing the control that early is likely to have catastrophic effect. So you'd want this transfer of execution to coincide with the last instruction in the loop, and therefore you'd want to postpone the issue of the return instruction by 5 (11 minus 5 delay slots minus 1 for instruction itself) cycles, which would give you SPKERNEL 2,1. [On side note one also has to ensure that there is execution port available for execution of the return instruction at that particular cycle. If there is none, then you'd have to postpone execution for even later.]

Important to note that "can be performed with SPLOOP 2" does not mean that you can simply replace 13 with 2 in the presented example. That would produce dead wrong result. The loop would have to be rearranged for lower iteration interval.

As for "SPLOOP 2" per se. For completeness sake one should say that there is one condition which would legitimate SPLOOP 13 and render SPLOOP 2 suggestion inappropriate. But I find it hard to imagine that such condition would have to be met. The condition is that second ldw instruction in the loop would have to load result written by stw instruction. Only then SPLOOP 13 would be a must. Is it actually case here?