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TMS320C6748 Bootmode SPI0 Flash SPI capture

Hi,

Would it be possible to have more details on the SPI interface described in spraat2f?

At what speed the host (master) should set the clock?

How is packaged the data on the SPI line please could you provide a capture or an exemple?

For exemple, for XMT_START (0x5853) how should look the SPI line of the Master (MOSI)?

0x00 0x00 0x00 0x00 0x00 0x00 0x53 0x58 0x00 0x00 0x00 0x00 0x00 0x00 0x53 0x58 0x00 0x00 ...

or

0x00 0x00 0x00 0x00 0x00 0x00 0x58 0x53 0x00 0x00 0x00 0x00 0x00 0x00 0x53 0x58 0x00 0x00 ...

or

0x53 0x58  0x53 0x58  0x53 0x58  0x53 0x58 ....

or

0x58 0x53 0x58 0x53 0x58 0x53 0x58 0x53...

thanks,

Eric

  • Here is extra information :

    At the moment I made few test trying to send a XMT_START but I never got any answer from the DSP. When I switch to other bootmode (SPI Flash) I can see activity from the DSP on its line.

    I am currently using a clock of 1MHz on the SPI.

    The Debug GEL files show the following (SPI0 Slave is correctly activated):

    C674X_0: GEL Output: ---------------------------------------------
    C674X_0: GEL Output: | BOOTROM Info |
    C674X_0: GEL Output: ---------------------------------------------
    C674X_0: GEL Output: ROM ID: d800k006
    C674X_0: GEL Output: Silicon Revision 2.0
    C674X_0: GEL Output: Boot pins: 18
    C674X_0: GEL Output: Boot Mode: SPI0 Slave
    C674X_0: GEL Output:
    ROM Status Code: 0x00000000
    Description:C674X_0: GEL Output: No error
    C674X_0: GEL Output:
    Program Counter (PC) = 0x11800EC0

    Is there something wrong in the way the XMT_START is packaged on my SPI line? Here is the capture of the 4 test I made. You can see that the DSP never answers (line is 0xFF) The code keep trying for 10 seconds.

      :

  • Eric,

    Based on the information that you have shared with us in your earlier e2e post, we are assuming that the device is configured in SPI Master boot mode.

    For SPI master boot, when the boot starts up, the bootloader comes up with PLL in bypass and the SPI clock at 800 Khz. After receiving the opcode to configure the PLL, the device will setup the PLL0 and PLL1 and then bump up the SPI clock to settings specified in the boot Image. The SPI clock limits(50Mhz) specified in the C6748 device datasheet and the flash device will apply while configuring the SPI clocks.

    For SPI slave boot, we recommend users to not use SPI clocks higher than 12.5 Mhz for reliable booting and that the initial transfers where the PLL has not been setup have sufficient delays to allow for device to complete initializing clocks.

    I don`t have scope shots handly to share at the moment but I try to see if we have captured something that I can share.

    Regards,
    Rahul
  • Hi Rahul,

    Yes this post is related to your suggestion of using a different bootmode.

    I currently set the Bootmode pins to mode #18/SPIO Slave. I am currently trying to implement the Master Host on the SPI.

    Since TI recommend a clock of 12.5MHz, I guess using a clock of 1Mhz should not be a problem?

    I did not ask in the previous question but what should be the level of the chip select sent by the master, Low or High? I tried different level and it did not seem to have an effect.

    thanks,
    Eric
  • Eric,

    Can you confirm that you are operating the SPI interface in 16 bit mode as specified in the Application notes.

    I found an old screen grab from Datacenter tool that we had used for debuging the SPI slave boot that might be useful for your setup. Please refer to it the SPI slave operates in 16 bit mode so the master needs to send 0x5853 followed by 0x0000 to allow the slave to respond.

    Hope this helps.

    Regards,

    Rahul

  • All SPI boot modes use the chip select 0 signal and the chip Select should go low during a SPI transaction as shown in the TRM.

    Also, in one of your screenshots, you have shown the SPI Enable pin which shouldn`t be connected. The devices need to be connect in 4 pin mode with clock, SIMO, SOMI and Chip select while interacting with the boot loader.

    Regards,
    Rahul

  • Hi Rahul,

    We were considering implementing the SPI0 Slave or SPI1 Slave bootmode but unfortunately the SPI enable pin is not connected on our custom board. I have to see if we can modify our board to connect the pin.

    Thanks for your help.

    Eric
  • Eric.

    I think you misunderstood my response. I meant the SPI enable pin shouldn`t be connected. Only clock, SPI SIMO ,SOMI and Chip select pins should be connected to the slave.

    Regards,
    Rahul
  • Hi Rahul,

    Yes I made a confusion.

    So I understand that SPI0_SCS[0] must be set to 0 while SPIO_ENA can reamin not connected.

    I read in sprufm4i.pdf that in SPI Slave mode the values of SPI0_SCS[1] to SPI0_SCS[5] are not use a slave select only the SPI0_SCS[0].

    thanks,
    Eric
  • Hi Rahul,

    I was wondering if you had any more of that screen grab.  I seem to have things working up to the point you show but then things stop working.  The start word synchronization works just like you've shown.  I send 0x5853 and then get a 0x5253 reply back.  My ping op-code synchronization also seems to be working.  I'll send 0x590B 0x5853 and get back 0x590B 0x5253; I send a random 32bits and get the same thing back that I sent; I send a 0x0001 0x0000 and get the same back as a reply.  It looks just like your example from the screen grab.  Everything is going perfect until I send my first AIS op-code.  I send 0x590D 0x5853 but what I get as a reply is 0x5253 0x0000 or 0xFFFF 0x0000.  I can't get op-code synchronization to work and I don't know why.

    I wanted to see further down your screen grab to see if you keep sending data as 16bit little endian or if you switch to 8 bit little endian.  I've referenced a TI AIS Parser called AIS_Util.cs and that code sends the start word synchronization, ping op-code synchronization, and op-code synchronization in 8 bit little endian.  When I try that it doesn't work.  Only 16bit little endian works but only up until the op-code synchronization

    Thanks,
    Steve.