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DDR2 initialization sequence - what is the purpose of the wait(1500) in the sample gel file ?

ixworks
Intellectual 880 points

There is a wait_soft() call at the end of this procedure.  Is there a status register that would work more appropriately for DDR2 configuration?

Also, its writing to reserved bits which aren't correct at power on.   Is this the M.O. for reserved bits?  What should DDR2 reserved bits be set to?  they are reserved, but R/W.  The gel file touches them which confuses me a bit. 

Thanks

    // Special reserved bits
    // Writes special reserved bits which are not correct at power on
    DDR_SDCFG    = (iSdcfg | 0x00530000 | TIMUNLOCK);
   
    // Lock DDR Bank timing
    DDR_SDCFG    = iSdcfg;

    // ReadLatency = CAS +1 with default bits in other positions and release rst
    DDR_DMCCTL  = (DDR_DMCCTL & 0xFFFFFFF8) | ( iCas + 1);
    DDR_DMCCTL  = (DDR_DMCCTL & 0xFFFFFFDF);

    Wait_Soft( 1500 );

    GEL_TextOut( "DDR2 Setup... Done.\n" );
}

  • 0
    TI__Guru** 116100 points
    Can you please tell me what is the processor ?
    I think its C6657 ?
  • 0
    TI__Mastermind 43660 points
    Hello,

    I am not clear what exact information you are looking for ? Which register you are referring for the reserved bits ?

    Regards,
    Senthil
  • 0
    TI__Mastermind 43955 points

    Hi ixworks,

    ixworks said:
    There is a wait_soft() call at the end of this procedure. Is there a status register that would work more appropriately for DDR2 configuration?


    In general, these type of calls are included to insert a delay in order to give sufficient time to the settings made in the previous instructions. In your code, it seems to be the instructions of setting the values for " DDR_DMCCTL "

    ixworks said:
    Also, its writing to reserved bits which aren't correct at power on. Is this the M.O. for reserved bits? What should DDR2 reserved bits be set to? they are reserved, but R/W. The gel file touches them which confuses me a bit.


    In general, as the name implies,  the reserved bits are the reserved ones and must be used as described in the document. Sometimes, while porting the gel files from one processor to another processor, these bits may be reserved in one processor and may be purposely used in another processor.

    Please check out the datasheet of the processor, map the register and understand the significance.
    Hope this clarifies!

    Meanwhile let me also have a look and get back.

  • 0
    TI__Guru* 84110 points

    ixworks,

    ixworks said:
    Also, its writing to reserved bits which aren't correct at power on.  ....  The gel file touches them which confuses me a bit. 

    I do not see any unusual writes to reserved bits. You will have to explain what you are concerned about, please, or is your question due to the comments that are included?

    ixworks said:
    DDR_SDCFG    = (iSdcfg | 0x00530000 | TIMUNLOCK);
    DDR_SDCFG    = iSdcfg;

    Please correct me if I am wrong, but the DDR_SDCFG writes only write 0's to the reserved bits in the SDCFG register, both times the GEL writes to those registers.

    ixworks said:
    DDR_DMCCTL  = (DDR_DMCCTL & 0xFFFFFFF8) | ( iCas + 1);
    DDR_DMCCTL  = (DDR_DMCCTL & 0xFFFFFFDF);

    These DMCCTL writes are read-modify-write lines so they write back the same value as read from all the bits including the reserved bit, other than the few bits that are cleared by the masking.

    ixworks said:
    Is this the M.O. for reserved bits?  What should DDR2 reserved bits be set to?  they are reserved, but R/W.

    I will address this to say that Reserved bits and Reserved field values and Reserved memory regions are to be avoided and never written to except as instructed in the documentation. There is nothing in the errata document about either of these two registers, so it is not clear what might be the concern that was considered in the comments.

    ixworks said:
    Is there a status register that would work more appropriately for DDR2 configuration?

    I do not see one, and I do not see any restriction in the DDR register programming that would require the delay. If you are having issues with your DDR functioning correctly, I recommend following the GEL file since it has been tested on boards for several years. And I also recommend following the documentation closely. When those contradict each other, we can try to find explanations but the GEL is experience-based so it is a good guideline to keep available. The documentation would be updated in any cases where some bits are not operating correctly out of reset, so these comments could have been put in for an early version of the device and the GEL was never updated. Or the GEL was updated with correct values but the comments were not updated.

    Regards,
    RandyP