Dear Ti:
I have a problem that how can i set my PLL frequencies. I set the PLL0_PLLM to a high value but my program can't run correctly. Now the setting is 18, which can set the pll0 to 456Mhz , it work good. but when i set it more than this num, like 23 in my .gen file, it will never run correctly.
but as the manual said,when my oscin is 24M, it can frequency doubling to 600MHZ
Long gao,
Please specify which device are you trying to set the PLL clocks on. From the 456Mhz setting, I suspect you are trying to configure C6748 or OMAPL138 device.
For C6748, you can simulate your clocks using the PLL clocking spreadsheet that we provide here:
In the XL file, you can setup PLL_EN to locked and then modify PLLM , PREDIV , POSTDIV and DIVx to simulate the PLL clock settings.
For 24 Mhz oscillator clock in, you can set the PLLM to 19 (0x14) and PRE and POSTDIV to 1 to get to 456 Mhz. However if you set the PLLM to 25 (0x19) then you need to set the POSTDIV to 2 and get to 300Mhz since maximum frequency is 456Mhz as shown below:
The formula always remains as SYSCLK1 = OSCIN * PLLM / (PREDIV * POSTDIV * PLLDIV1) provided PLLOUT < 600 and SYSCLK1 < 456 Mhz
Regard,
Rahul
