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TARGET ABORT DUE TO SYSTEM ERROR

vaishnavi gujjula
Prodigy 240 points

HI,

   I am  getting Target abort due to system error while generating PCI Interrupt. In configuration read registers we are setting SERR bit of (PCICSRMIR Register).Is there any configuration is there to avoid System Error (SERR). At slave side I am generating PCI interrupt,But at Master side I am unable to see that interrupt.Is this SERR error may cause that not to detect that PCI interrupt  (DSPINT)which is generated by slave ? Am I missing anything to avoid SERR error? Can you please tell the reason why it is Aborting.

Thanks in advance.

  • 0
    TI__Guru 65405 points

    Hi Vaishnavi,

    I've forwarded this to the PCI experts. Their feedback should be posted here but could you give details about the software running on your board and what exactly is your hardware?

    Can I consider the issue is same as

    If it is true let's combine both thread.



    BR
    Tsvetolin Shulev

  • 0 in reply to Cvetolin Shulev-XID
    Prodigy 240 points
    Hi ,
    Thanks for reply .Both are belongs to same thread (PCI INTERRUPT and Target abort) .We are using two C6455 DSP's. One DSP will be in signal processor and one dsp will be in RC .In our case SP is a slave and RC is a master .
    Slave Dsp is generating INTA signal .At first INTA will be high ,after interrupt settings slave will generate active low interrupt signal (INTA).In between master and slave we are using PLX9056 chip .Will slave generates only INTA signal ?or else,Will it generates any other signals at the same time to sense the master DSP? Slave is generating INTA signal ,But that signal is not detecting by Master DSP. Is master need any other signal other than INTA signal to generate DSPINT? By taking INTA signal Master should generate DSPINT ,But why Master DSP is not sensing . Is there another settings required to be set at slave and master side to generate DSPINT?Can you please tell the reason.
    I am getting Target abort due to system error while generating PCI Interrupt. In configuration read registers we are setting SERR bit of (PCICSRMIR Register).Is there any configuration is there to avoid System Error (SERR). Is this SERR error may cause that not to detect that PCI interrupt (DSPINT)which is generated by slave ? Am I missing anything to avoid SERR error? Can you please tell the reason why it is Aborting.


    We are Using PCISTATSET & PCIHINTSET registers at SP side to generate interrupt. At RC side if we set PCIBINTSET register the interrupt should detect by RC . At SP side successfully we are able to generate interrupt.But we are not able to see the interrupt at RC side .How to generate DSPINT interrupt at RC side . Is there any other configuration is required to generate interrupt at PLX chip side or at RC side?

    we setting registers as follows:

    AT SP side:

    PCISTATSET=0x01000000

    PCIHINTSET=0x01000000

    AT RC side:

    PCIBINTSET=0x81000000(31st bit is DSPINT).

    Can you please tell how INTA will be connected to PLX chip ,and how this PLX chip will generate DSPINT interrupt to the DSP at RC side.

    Thanks in advancce,


    Regards,
    vaishnavi.