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TMS320C6748: SDMMC writer in OMAP-L138_FlashAndBootUtils_2_40

Part Number: TMS320C6748

#1. In the function LOCAL_GetAndWriteFileData(), why insert such a long delay after between write a block and read back for verification?

// Verify the data written, one block at a time 

for (i = 0; i< numBlks; i++)
{
if (SDMMC_MEM_writeBytes(hSdmmcMemInfo,
destAddr,
hSdmmcMemInfo->hSDMMCInfo->dataBytesPerBlk,
&appPtr[i*hSdmmcMemInfo->hSDMMCInfo->dataBytesPerBlk]) != E_PASS)
{
DEBUG_printString("\tERROR: Writing SDMMC failed.\r\n");
return E_FAIL;
}

UTIL_waitLoop(100000);

if (SDMMC_MEM_verifyBytes(hSdmmcMemInfo,
destAddr,
hSdmmcMemInfo->hSDMMCInfo->dataBytesPerBlk,
&appPtr[i*hSdmmcMemInfo->hSDMMCInfo->dataBytesPerBlk],
gMemRx) != E_PASS)
{
DEBUG_printString("\tERROR: Verifying SDMMC failed.\r\n");
return E_FAIL;
}
destAddr += hSdmmcMemInfo->hSDMMCInfo->dataBytesPerBlk;
}

#2. In the SDMMC_MEM_writeBytes, there is status checking already. 

// Wait until status shows done
while (SDMMC->MMCST0 & SDMMC_MMCST0_DATDNE_MASK == 0);

#3. But if remove the delay UTIL_waitLoop(100000); the SDMMC->MMCST0 will be 0, program will wait in the loop forever.

Uint32 SDMMC_readNWords(SDMMC_InfoHandle hSDMMCInfo, Uint32 *data, Uint32 numofBytes)
{
DEVICE_SDMMCRegs *SDMMC = (DEVICE_SDMMCRegs *) hSDMMCInfo->regs;
Uint16 i=0,j=0;
Uint32 status;
Uint32 fifoReadItrCount, wordItrCount;

// Setup counters for fifo iterations and word iterations
fifoReadItrCount= numofBytes >> hSDMMCInfo->dataBytesPerOpPower2;
wordItrCount = hSDMMCInfo->dataBytesPerOp >> 2;

for(i=0; i<fifoReadItrCount; i++)
{
// Wait for DRRDY or some kind of error/timeout
do
{
status=SDMMC->MMCST0;
if (status & (SDMMC_MMCST0_CRCRD_MASK | SDMMC_MMCST0_TOUTRD_MASK))
{
return E_FAIL;
}
}
while( (status & SDMMC_MMCST0_DRRDY_MASK) == 0 );

// Read the data, one word at a time
for(j=0; j<wordItrCount; j++)
{
*data++ = SDMMC->MMCDRR;
}
}
return E_PASS;
}

#4. if remain the delay, then MMCST0 return 0x400. then read back data from fifo.

Question: 

Why need such a long delay? how to determine the delay cycle needed?