Hi,
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Hi,
70 clock cycles is not unrealistic for the C6748 to work the GPIO. At least it is in the ballpark of taking lots of cycles to do it. The DSP is designed to do math really well and makes system tradeoffs that allow a strong reliable design to work with a wide variety of internal peripherals on the internal buses.
How are you measuring the 70 clock cycles? From what measurable start to what measurable end? It is extremely difficult to get an accurate measurement from a DSP instruction execution to an external pin change because of the delays between the two, going both ways.
How fast do you need the GPIOs to run? Do you need to be going both directions simultaneously, plus generate a clock and select line?
The C6748 has two SPI ports with multiple chip selects already on the part. If you need a third or fourth SPI port, how much processing capability are you willing to give up for bit-banging the SPI pins?
Regards,
RandyP