TMS320C6746: Why is it that the model type of C6746 DDR_D/DOS pins in the IBIS model is defined as 3-state?

j-breeze

Part Number: TMS320C6746

Hi Champs,

I've got a C6746 ZWT IBIS model(SPRM374B) and I see that the model type of C6746 DDR_D[15:0]/DOS[1:0] pins in the IBIS model is defined as 3-state, not I/O.
The pin type of those pins is defined as I/O in the C6746 Datasheet(SPRS591F).
So, Could you please let me know why the model type is defined as 3-state, not I/O?

Regards,
j-breeze

over 7 years ago

0 Cvetolin Shulev-XID over 7 years ago

TI__Guru 65405 points

Hi J-breeze,

I've forwarded this to the hardware experts. Their feedback should be posted here.

BR
Tsvetolin Shulev

0 Senthilkumar Srinivasan over 7 years ago

TI__Mastermind 43660 points

Hello,

I am not sure why the DDR data and DQS pins are considered as tri-state in IBIS. I will try to check with IBIS and clarify you.

Regards,
Senthil

0 j-breeze over 7 years ago in reply to Senthilkumar Srinivasan

Mastermind 7560 points

Hi Senthil,

Thank you for your support. I'm hoping to hear from you.

Regards,
j-breeze

0 j-breeze over 7 years ago in reply to j-breeze

Mastermind 7560 points

Hi Senthil,

It would help me if I could get your feedback by 31th.

Regards,
j-breeze

0 Senthilkumar Srinivasan over 7 years ago in reply to j-breeze

TI__Mastermind 43660 points

I have sent an email to IBIS expert. Waiting for his response.

0 j-breeze over 7 years ago in reply to Senthilkumar Srinivasan

Mastermind 7560 points

Hi,

Is there any feedback from the IBIS expert?

Regards,
j-breeze

0 Senthilkumar Srinivasan over 7 years ago in reply to j-breeze

TI__Mastermind 43660 points

Here is the response from IBIS team,

DDR data signals use IO buffer that is 3-state. For example, when data signals are transitioning from read to write, or write to read, the bus will be tri-stated, so the IBIS model reflects the true IO buffer behavior.

Regards,
Senthil

0 j-breeze over 7 years ago in reply to Senthilkumar Srinivasan

Mastermind 7560 points

Hi Senthil,

Thank you for your support. But I can not understand the answer you gave me.
Could you explain it more in detail? Dose it mean I can use [POWER_clamp]/[GND_clamp] I-V data of the 3-state as the input?

Regards,
j-breeze

0 j-breeze over 7 years ago in reply to j-breeze

Mastermind 7560 points

Hi Senthil,

Could you please send my question to the IBIS expert again?

Regards,
j-breeze

0 Senthilkumar Srinivasan over 7 years ago in reply to j-breeze

TI__Mastermind 43660 points

As long as the 3-state is not driven, basically in the high impedance state, it will be treated as an input.

Regards,
Senthil

0 j-breeze over 7 years ago in reply to Senthilkumar Srinivasan

Mastermind 7560 points

Hi Senthil,

I found the other IBIS model definition of DDR_D[15:0]/DOS[1:0] pins below. It's for DM6437 and defined as I/O, not 3-state.
Moreover, It was updated from 3-state to I/O. Could you please let me know which definition is correct?

o DM6437 ZWT IBIS Model (Rev. B) [sprm230b Jun10]

    - Line 14~16

    3.0: 3rd release, 09/09/2008
           updated buffer model from 3-state to I/O for
           BSSTL18WGFZ

    - Line 1618~2482

      [Model]            BSSTL18WGFZ
      Model_type         I/O

Regards,
j-breeze

0 j-breeze over 7 years ago in reply to j-breeze

Mastermind 7560 points

Hi,

Any comment would be appreciated.

Regards,
j-breeze

0 Senthilkumar Srinivasan over 7 years ago in reply to j-breeze

TI__Mastermind 43660 points

j-breeze,

The DM6437 is from different family and i am not sure why it was updated from 3-state to I/O. Please refer the information from IBIS team which i posted earlier.

Regards,
Senthil

0 j-breeze over 7 years ago in reply to Senthilkumar Srinivasan

Mastermind 7560 points

Hi,

Could you please send my question about the DM6437 IBIS model definition to the IBIS expert?
If not, I'd like to start a new thread on the definition if you don't mind?

Regards,
j-breeze

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TMS320C6746: Why is it that the model type of C6746 DDR_D/DOS pins in the IBIS model is defined as 3-state?