TMS320C6748: L2 allocation registers on C6748

Never used L2 other than just plain memory but I have heard of others configuring it as cache. So it should not be reserved. The details for these registers are in SPRUFK5x, TMS320C674x DSP Megamodule Reference Guide, Chapter 4 Level 2 Memory and Cache.

Oops. I did not see that you meant the allocation registers:
0x0184 2000 L2ALLOC0 L2 allocation register 0
0x0184 2004 L2ALLOC1 L2 allocation register 1
0x0184 2008 L2ALLOC2 L2 allocation register 2
0x0184 200C L2ALLOC3 L2 allocation register 3
Sorry about that.

Google is your friend. It would seem L2ALLOCn was last documented for the C64x,
spru610c
TMS320C64x DSP Two-Level Internal Memory Reference Guide
February 2006
6.3 L2 Allocation Registers (L2ALLOC0−L2ALLOC03)

Also mentioned in an really old version of SPRU190D, February 2001. Removed in later versions.

No idea if these registers are really reserved on the C6748. Your fellow TI guys can comment.

Hi Norman,

Thank you very much.

Anybody can confirm this?

Thanks.

Rgds
Shine

The usage of L2ALLOCn is detailed in the EDMA document, spru234c, "TMS320C6000 DSP Enhanced Direct Memory Access (EDMA) Controller Reference Guide". Applies to the C64x again.

Shine,

Since Norman was able to find the older documents that described L2ALLOCn for the C64x devices, what then is the concern or reason for the inquiry?

Are you in a position to test the contents of those registers in CCS? If you write 0xffffffff to them one at a time, what do you read back? Same for some other patterns, to test the existence of a read/write register at each location, possibly 3 bits in length?

The L2ALLOCn registers have no meaning after the C64x. In the C64x+ and later devices, L2 cache accesses no longer go through the EDMA engine but have the MDMA port on the megamodule for getting onto the internal switch fabric.

Regards,
RandyP