TMS320C6746: Why are the DDR2 DDR_D IBIS model definitions b/w C6746 and DM6437 different?

j-breeze

Part Number: TMS320C6746

Hi Champs,

I asked before, but it was for different families. So, I'd like to start a new thread.
I posted the same thread to DM64x DaVinci Video Processor Forum because I'm not sure how I can ask questions related to different families.

The model type of C6746 DDR2 DDR_D[15:0] pins in the IBIS model is defined as 3-state, not I/O.
On the other hand, the model type of DM6437 is defined as I/O, not 3-state.

The I/F is the JEDEC standard. So, could you please let me know which definition is correct?

Regards,
j-breeze

over 7 years ago

0 Cvetolin Shulev-XID over 7 years ago

TI__Guru 65405 points

Hi J-breeze,

I've forwarded this to the design experts. Their feedback should be posted here.

BR
Tsvetolin Shulev

0 Bill Taboada over 7 years ago

TI__Mastermind 42545 points

Hi j-breeze,

The IBIS model describes the behavior of the buffers used in the design of the part. These buffers can be different from part to part based on a number of reasons. Whether it's a change in process level or the fact that the part was developed by a different group within TI, there will sometime be differences. The IBIS model is delivered by the design team for each part to describe the behavior that will be observed. While all of these implementations will meet the standard, they are not identical in behavior.

Regards,

Bill

0 j-breeze over 6 years ago in reply to Bill Taboada

Mastermind 7560 points

Hi Bill,

Thank you for your reply.

So, you mean that I can verify the C6746 DDR2 DDR_D[15:0] I/O pins as input buffers by using the IBIS model in which the pins are defined as 3-state?
I'd like to make sure of it.

Regards,
j-breeze

0 j-breeze over 6 years ago in reply to j-breeze

Mastermind 7560 points

Hi Bill,

Your prompt reply would be greatly appreciated.

Regards,
j-breeze

0 j-breeze over 6 years ago in reply to j-breeze

Mastermind 7560 points

Hi Bill,

I was wondering if you could answer my question ASAP?

Regards,
j-breeze

0 Bill Taboada over 6 years ago in reply to j-breeze

TI__Mastermind 42545 points

Hi j-breeze,

I'm currently out of the office. I've forwarded your request to my coworkers.

Regards,

Bill

0 Tom Johnson 16214 over 6 years ago in reply to Bill Taboada

TI__Mastermind 46460 points

j-breeze,

You have asked why IBIS models are different between 2 separate, unrelated parts. Bill has answered that question. Are you really trying to determine how to model the BIDI DDR data pins on the C6746 in input mode as opposed to output mode?

Tom

0 Tom Johnson 16214 over 6 years ago in reply to Tom Johnson 16214

TI__Mastermind 46460 points

j-breeze,

We provide IBIS models for signal integrity evaluation. We do not provide IBIS models to support DDR timing analysis. As such, the VIN specs in the model are not relevant. This effectively makes the models align. You can run your C6746 DDR read simulation with the data buffers in the HI-Z condition. This will provide the package and input RLC parasitics needed to perform your signal integrity analysis.

Tom

0 j-breeze over 6 years ago in reply to Tom Johnson 16214

Mastermind 7560 points

Hi Tom,

Thank you for your advice.

Regards,
j-breeze

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TMS320C6746: Why are the DDR2 DDR_D IBIS model definitions b/w C6746 and DM6437 different?