I am using DSP C6748 SPI to communicate with a real-time clock with SPI inteface.
Sometimes, the communication does not work as expected.
I was puzzled about setup/hold time of data-SCLK of the SPI . On the SPI registers, it is not possible to change data-SCLK setup/hold times.
In SPI, is I/O data driven before one quarter of SPI SCLK period providing a setup and hold times of 0.25/SCLK be default?
Best regards.
Izzet