TMS320C6746: OSCIN greater than 30 Mhz

Hi Robert,

I've forwarded this to the HW design experts. Their feedback should be posted here.

BR
Tsvetolin Shulev

Randy,

Thanks for the reply. The bottom line for this request is to facilitate a 10 Khz sample rate from the TLV320AIC3254 codec that the TMS320C6746 is mated with. The McASP on the 6746 provides the master bit clock to the codec, via the AHCLKX line to it. The codec is recommended to oversample by a factor of 128, and then has two more dividers to try and get the desired sample rate:

codec sample rate = AHCLKX / ( 128 * NADC * MADC )

and we can't get a high enough AHCLKX out of the McASP, given that formula, and desire to hit 10 kHz exactly, with a 30 Mhz or lower OSCIN/crystal.

The McASP AHCLKX is driven by PLL0_AUXCLK, which is a direct connect to the OSCIN frequency, so can never be higher than that (HCLKXDIV and HCLKRDIV value of 0 ). If there were some way to multiply that up, from OSCIN, we wouldn't need a higher crystal.

This would be for actual product development, subject to expected customer use and environment variations, so we couldn't risk going beyond spec, based on your caution provided. So will probably have give up on the 10 kHz codec sample rate.

Please advise, if you can see any flaw in my logic above, or see any other angle to accomplishing this.

Robert

Robert,

Can you supply an external input clock to the McASP?

Regards,
RandyP

Randy, Prabhu,

Thanks for the replies, and external clock suggestion.  I don't think that will be an option, but have to check with my hardware engineer tomorrow, to confirm.  Please see comments below.

Rahul Prabhu said:

Robert,

If AIC codec is the slave and McASP ACLKX drives the sampling rate.

McASP AHCLKX drives MCLK on the codec.

Rahul Prabhu said:

Your description is incomplete what is the eventual bit rate you need to get to ?

Whatever bit rate can be divided down to get 10 kHz sample rate from the TLV320AIC3254.  Per my last reply, on the codec, it's defined as the following:

    sample rate = MCLK / ( AOSR * NADC * MADC )

where AOSR is highly recommended to be 128.  I cannot achieve 10 kHz with any C6746 crystal that is 30 Mhz or below.  With 32 Mhz, I can set HCLKXDIV and HCLKRDIV on Mcasp to 24, which gives AHCLK of 1.28 Mhz.  With AOSR = 128, and NADC and MADC = 1, we get 10 Khz.

Rahul Prabhu said:

Is McASP is the Master driving the clock or is it the slave receiving the clock from the codec?

confused by your question, but as mentioned, McASP AHCLKX drives coded MCLK.  I believe that would be McASP as master, and codec as slave then.

Rahul Prabhu said:

Look at (AHCLKXCTL) This will allow you to get AHCLKX from external source instead of using PLL0_AUXCLK.

Ok, yes, I have seen that.  But as mentioned, I don't believe using an external source is an option at this time.  Our C6746 target is already made, in PCB format, and that level of change may not be supported, from time and complexity standpoint.  However, changing the crystal would have been supported, as much easier PCB change.

Rahul Prabhu said:

I highly recommend that you take a look at the interactive clocking spreedsheet that we provide here and simulate your usecase.
processors.wiki.ti.com/.../AM18xx

The spreedsheet has a tab for McASP that helps visualize the Register settings and McASP clocking.

I downloaded and examined that spreadsheet, but saw no tab for McASP.  But I understand what you say from section 7.3.6 of the SPRUGM7D (April 2010).  Although that is OMAP-L138, it is same clocking and McASP, and the only place I have seen that talks about PLL0_AUXCLK, as input for the TX/RX reference clock (and also discusses the external option)

Rahul Prabhu said:

In the even that you can`t generate high enough AHCLKX from PLL0_AUXCLK, there is an option to get the clock from external source which you can explore.

Right, but probably not going to be an option for us.  But thanks for the suggestion.  Any other comments/suggestions welcome.

Regards,

Robert

Robert56682 said:

Rahul Prabhu

I highly recommend that you take a look at the interactive clocking spreedsheet that we provide here and simulate your usecase.
processors.wiki.ti.com/.../AM18xx

The spreedsheet has a tab for McASP that helps visualize the Register settings and McASP clocking.

I downloaded and examined that spreadsheet, but saw no tab for McASP.  But I understand what you say from section 7.3.6 of the SPRUGM7D (April 2010).  Although that is OMAP-L138, it is same clocking and McASP, and the only place I have seen that talks about PLL0_AUXCLK, as input for the TX/RX reference clock (and also discusses the external option)

I ended up finding the speedsheet you mentioned, with the McASP tab, at that website link.  But it appears to just confirm what I already knew and calculated ;)  Problem still remains.

Regards,

Robert

After speaking with my hardware engineer, it is confirmed that supplying an external clock to the McASP would not be a trivial change at this point. But one that we'll continue to investigate/consider. The external clock would need to be generated by the C6746 itself, so I'll have to see if there is a resource available on the processor to get the type of clock rates I've discussed, i.e. multiples of 1.28 Mhz. If anyone has any ideas, they'd be appreciated, or else I'll mark this thread as answered, as the original question was (strongly advised against a crystal exceeding the 30 Mhz limit).

Thanks,
Robert

Cvetolin Shulev-XID said:

Hi Robert,

I've forwarded this to the HW design experts. Their feedback should be posted here.

BR
Tsvetolin Shulev

Hello,

If you do hear back from the HW design experts, please post their feedback ... still interested in that.

Thanks,

Robert

Robert,

One other option that falls within the specs of this device is 19.2 MHz. I am checking with our systems team if there is any risk associated with this OSCIN value but came across this article that you may use for your consideration.
processors.wiki.ti.com/.../C674x_crystal_and_pll_frequencies

Please look at the care abouts for USB and Ethernet and let us know if this could work with your design.

Regards,
Rahul

Rahul Prabhu said:

Robert,

One other option that falls within the specs of this device is 19.2 MHz. I am checking with our systems team if there is any risk associated with this OSCIN value but came across this article that you may use for your consideration.
processors.wiki.ti.com/.../C674x_crystal_and_pll_frequencies

Please look at the care abouts for USB and Ethernet and let us know if this could work with your design.

Regards,
Rahul

Hello,

I'm not seeing how 19.2 Mhz gives a 10 kHz sample rate.  We have four divider factors involved

    1. HCLKDIV (HCLKRDIV and HCLKXDIV) to get AHCLK from the McASP, which is the master bit rate to the codec.  AHCLK = [ OSCIN / ( HCLKDIV + 1 ) ]

    2. AOSR on the codec, which is recommended to be 128 always

    3. NADC on the codec

    4. MADC on the codec

Putting all together:

    sample rate = OSCIN / [ ( HCLKDIV + 1 ) * 128 * NADC * MADC ]

I see no way to get 10 kHz from that equation, with 19.2 Mhz.

Please advise, if you do.

Robert

Hi Rahul
Forwarded this thread to me and I am reconfirming what Rahul and Randy have mentioned ( I believe you were looking for a final confirmation on this) - 32 MHz is outside datasheet spec, not tested, never used by any customer , therefore we cannot support or endorse it.

I am hoping between using an external clock or further figuring out potential solutions from audio converter experts you may find an alternate solution.

Please also note that we do not recommend using CLKOUT as a clock source , as mentioned in the schematic checklist

processors.wiki.ti.com/.../_AM1x_Schematic_Review_Checklist

Regards
Mukul

Rahul Prabhu said:

In your previous post, you mentioned that you are looking to set the sample rate to multiple of 1.28 Mhz so from the SOC perspective. A 19.2 Mhz clock can be divided down to 1.28 MHz and 3.84 MHz. This is how we sample audio at 48 or 44.1 Khz sampling rates on our EVMs using AIC31xx codec.

I missed that one, that the 19.2 can be divided down to get the 10 kHz sample rated desired:

OSC	19200000
CLKRDIV	1
HCLKRDIV	14
AHCLKX	1280000
ACLKX	640000
AFSX	10000
NADC	1
MADC	1
AOSR	128
Sample Rate	10000

However, I'll have to confirm that we can hit our clocking specs for everything else on the target, using this clock.

Rahul Prabhu said:

I am not a AIC codec expert but my understanding from configuring the AIC31xx codec is that when the CODEC is configured as the slave, it uses the bit clock from the the master as the sampling rate. The MADC, NADC and AOSR is applied only when AIC is the clock master and drives the master clock (using an external crystal). Please confirm this understanding on the Audio converter forums.

Taken from SLAA408A, TLV320AIC3254 Application Reference Guide:

"In summary, Codec_Clkin which is either derived directly from the system clock source or from the internal PLL, divided by MADC, NADC and AOSR, must be equal to the ADC sampling rate ADC_or fS. The
codec_clkin clock signal is shared with the DAC clock generation block. CODEC_CLKIN = NADC * MADC * AOSR * ADC_FS"

So there is no concept of master/slave, as understood, and confirmed in practice.  It simply takes the source of the input clock (McASP AHCLK in my case), and divides it down by NADC, MADC and AOSR, always.

Thanks,

Robert

Mukul Bhatnagar said:

Hi Rahul
Forwarded this thread to me and I am reconfirming what Rahul and Randy have mentioned ( I believe you were looking for a final confirmation on this) - 32 MHz is outside datasheet spec, not tested, never used by any customer , therefore we cannot support or endorse it.

Got it, thanks.

Robert

Thanks for providing us the perspective from the AIC32xx side. Please let us know if you need any further assistance regarding this issue.
Please close the issue when you confirm the clocking specs.

Rahul Prabhu said:

Thanks for providing us the perspective from the AIC32xx side. Please let us know if you need any further assistance regarding this issue.
Please close the issue when you confirm the clocking specs.

Will do.  One follow-up question - would you (or anyone) know of a preferred or recommended supplier of this 19.2 Mhz crystal?  Our current manufacture doesn't produce a crystal at that frequency.  

Thanks,

Robert

Robert
We will check, usually our product group is likely not going to have good data on this , as we are not in heavily in the business of making boards (post EVM design).

This is perhaps better addressed by the customer community here..

19.2 MHz is widely used especially on these devices where they are used in portable mobile radio space, but most of those customers have external clock sources (not crystals).
Do also note that when picking between crystal vs external oscillators - keep the "2.1.4 System-Level ESD Immunity Usage Note" usage note in mind.

Regards
Mukul