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CCS/TMS320C6748: HPI

Part Number: TMS320C6748

Tool/software: Code Composer Studio

  • FPGA configuration procedure:
  1. Initialization procedure:  HPIC  configuration , write 16‘h0060 to HPIC twice;
  2. HPIA  configuration ,  write address 32’h80010000 to HPIA  (the  first half-word is  16’h8001, the second half-word is 16’h0000) ;  
  3. Write data to HPID (first 16bit and then next 16bit); 
  4. Step 2&3  loop.

 

Figure1

As shown in the figure 1 ,

port0 is the DSP’s feedback :UHPI_HRDY;

port1 is the DSP’s feedback :UHPI_HINT;

port2  is  the FPGA part’s  output: UHPI_HR/W, the value is 0, meaning write operation;

port3 is  the FPGA part’s  output: hds1, and  value of hsd2 is  1;

port4 is the  simulation on FPGA of  DSP  internal  signal: Internal HSTRB ,when UHPI_HCS equals   0, Internal HSTRB equals  hds1;

port5 is  the FPGA part’s  output: UHPI_HCS,the value is 0;

port6 is  the FPGA part’s  output: UHPI_HHWIL;

port[8:7] are  the FPGA part’s  output : UHPI_HCNTL[1:0];

port[24:9] are  the inout : UHPI_HD[15:0].

 

question:

When writing the HPIC, it works correctly. The value has been written into the DSP register (can be seen from CCS)

 

But, when writing the HPIA, the DSP seems does not acknowledge the write operation (the UHPI_HRDY keeps low). So HPIA is not written correctly.

 

Then, when writing the HPID, the DSP acknowledges (UHPI_HRDY rise at the 2nd half word, then falls to low again). But the value is not written into the RAM address, since HPIA is not correct.

 

So, our question is why the timing of HPIC and HPID is right, but HPIA cannot be written.

 

DSP configuration :

Figure2

0x01E1000C is GPIO ENABLE REGISTER, equals 0, which means the function of HPI

0x01E10010 is GPIO DIRECTION 1 REGISTER, setting to 0, which means HD is the DSP’s input

0x01E10030 is HPIC, can be written in normally.

0x01E10034 is HPIAW, can’t be written in.

0x01E10038 is HPIAR, can’t be written in

PINMUX_REG_13/PINMUX_REG_14 PINMUX_REG_15 PINMUX_REG_16 enable the function of HPI

HPIENA of  CFGCHIP1  has enabled, HPIBYTEAD is  set to word address(byte address has also been set once)

 

note:the clk  of HPI  on FPGA is  40M, chipscope  sampling  clk is 200M; the clk  of HPI  on DSP is  40M 75M.

  • I've forwarded this to the system experts. Their feedback should be posted here.

    BR
    Tsvetolin Shulev
  • Thanks,waiting for your good news
  • error correction: the clk of HPI on DSP is 75M.
  • We  hope  someone can help  us

  • Hi
    Sorry for the delay - I appreciate the detailed post you put for your problem.
    I will need to ask around on this, there are limited expertise left on HPI peripheral.
    Can you see if the following thread helps

    e2e.ti.com/.../362381

    i believe you are writing to Shared RAM? however see if the addressing needs to be changed?

    Regards
    Mukul
  • Hi

    Thanks  for your help.

    And yes,we are writing to the shared RAM.  32’h80010000 is the first address .It will change by setting.

    Regards

    Yin

  • Why are you writing 0x0060 to HPIC? That does not look like a valid value from reading the reserved bits. The "all-0" value would be 0x0048, or 0x00C8 if HPIRST is still reading as a 1. Am I missing something?

    Have you tried writing to the HPIRST bit from the DSP-side to cause a reset? You could test it out by writing a 1 and then a 0 to see if anything changes.

    Please use a different address so you can confirm the address bits are not reversed. 0x8001 is the same either way.

    Similarly, try all of the four combinations of HCNTL[1:0] while observing the registers in CCS. And use interesting addresses and data to confirm the lines are correct.

    Confirm that you have followed all the steps in the Initialization section in the HPI User's Guide.

    The HRDYn signal is not an acknowledge signal, but is a wait signal. There is generally no reason for HRDYn to go high to cause a wait condition when writing to HPIC or HPIA. These are both internal registers with nothing to stall their access, whether reading or writing. When writing data, there is often a short stall from HRDYn when the second half-word is written since that is the time that the data is sent to the internal logic to cause the write or read to occur. In the case of a read, HRDY can be high for several cycles if a lot of time is required to go get the data from a slow location like external memory.

    Those are some thoughts to look at while waiting for the experts to reply.

    Regards,
    RandyP
  • Hi ,Randyp

    Thanks  for your help.

    We have changed HPIC value to  0x0048 ,and it solve our problem.

    Regards

    Yin