Hi,
My objective is to map UART1 transmit and receive events to queue 1 of EDMA3 channel controller 0.
I have something like
CSL_FINST( EDMA3->DMAQNUM[ EDMA_QUEUE_RX_UART1 ], EDMA3CC_DMAQNUM_E0, Q1 );
CSL_FINST( EDMA3->DMAQNUM[ EDMA_QUEUE_TX_UART1 ], EDMA3CC_DMAQNUM_E1, Q1 )
in my code where EDMA_QUEUE_RX_UART1 and EDMA_QUEUE_TX_UART1 being 1.
according to TRM , the field description is this.
As UART1 RX and TX events are events 12 and 13, I quite not sure how do I map/configure it in DMAQNUM register?
Regards
Parul Bhatt