C6455 restart or reload problem & EDMA3 efficiency

GANG ZHANG48047

Other Parts Discussed in Thread: TMS320C6455

Hi, everyone. My board is composed of 4 DSP(TMS320C6455) and 4 FPGA(XC5VLX50T), 1 DSP and 1 FPGA is a pair. DSP connects with FPGA via EMIFA interface. DSP read/write data from/to a dual RAM in FPGA, EMIFA worked at 100MHz and EDMA3 are used as read/write data engine. as figure below shows.

When I debug my board, there are some strange phenomenon that confuse me.
1. when the board first powered up, i run my DSP program of the 4 pairs at the same time, pair 1,2,4 run very well. The third pair can't run(i sampled EMIFA signal with Xilinx chipscope, i found that EMIFA signal was error--at some times, CE4 was high at the time it should be low), but when i restart or reload my program, it could run very well. what i wanted to ask is that does DSP chang its core status when i restart or reload program ? Does DSP initialization need more time before execute my program ?

2. I sampled EMIFA signals with Xilinx chipscope: After power up, i execute my program at the first time, I found that DSP used almost 100 clock cycles to read/write a 32bit data from/to FPGA dual RAM. But when I restart or relaod my program, it can read/write a 32bit data in a clock cycle. This phenomenon can happened in one pair, two pairs, three pairs or four pairs. It is random. What is the reason ? figure below is one example.

over 13 years ago

0 GANG ZHANG48047 over 13 years ago

Intellectual 875 points

I attached my DSP gel file and C source files.

8686.gel&c files.rar

0 one and zero over 13 years ago in reply to GANG ZHANG48047

TI__Genius 17676 points

Hi,

this sounds a marginal startup issue. This is hard to answer remotely but I can give you some hints where to look at:

1. Is PLL stable before releasing the device from reset (see datasheet for requiremens to be followed)

2. Check power sequencing (see datasheet for requiremens to be followed). Are the voltage rails stable?

Kind regards,

one and zero

0 GANG ZHANG48047 over 13 years ago in reply to one and zero

Intellectual 875 points

Hi,one and zero, thanks for your reply. For your suggestions, I checked the power sequencing and the reset status of my board. They are described as follows:
1. I followed the Power-Supply Sequence in Figure7-5 described in SPRH276H,and I set both of the parameters tsu(DVDD33-DVDD12) and tsu(CVDD12-ALLSUP) to about 2ms in my board.
2. As the reset signals: after 1.8V supply is stable, /RESET pin stays low for about 20ms; after /RESET is deasserted, /POR pin stays low for about 40ms.

I also have some questions as follows:
1. You point out that PLL should be stable before the device is released from reset, I think this 'reset' is the /POR pin. Does /POR and /RESET pin have sequence to be deasserted from low ? In my design, I load my GEL file which is used to configure PLL1 after DSP power up. Does this operation affect DSP's internal status especially the stable of PLL1 ? How can I know if PLL1 is in its stable status?

2. In my original GEL file, I added the following setences after "*(int *)PLLCTL_1 = (0x00000001);"(PLLCTL_1 = 0x029A0100)
     for (i=0;i<20000;i++);//delay
     *(int *)PLLCTL_1 = (0x00000041);
     for (i=0;i<20000;i++);//delay
  Are these setences helpful for PLL1's stable?

3. In my program, there is no operation to PLL1 registers. I only execute the GEL after power up and I restart or reload my program with no related GEL operations. how could my program run well after restart or reload .out file? I still have no idea of this phenomena.

Thank you very much again!

0 GANG ZHANG48047 over 13 years ago in reply to GANG ZHANG48047

Intellectual 875 points

can anyone else help me?

0 GANG ZHANG48047 over 13 years ago in reply to GANG ZHANG48047

Intellectual 875 points

my problem is still not resolved, help me....

0 one and zero over 13 years ago in reply to GANG ZHANG48047

TI__Genius 17676 points

Hi,

The following sequence must be followed during a Power-on Reset:
1. Wait for all power supplies to reach normal operating conditions while keeping the POR pin asserted
(driven low).
While POR is asserted, all pins will be set to high-impedance. After the POR pin is deasserted (driven
high), all Z group pins, low group pins, and high group pins are set to their reset state and will remain
at their reset state until the otherwise configured by their respective peripheral. All peripherals, except
those selected for boot purposes, are disabled after a Power-on Reset and must be enabled through
the Device State Control registers; for more details, see Section 3.3, Peripheral Selection After Device
Reset.
2. Once all the power supplies are within valid operating conditions, the POR pin must remain asserted
(low) for a minimum of 256 CLKIN2 cycles. The PLL1 controller input clock, CLKIN1, and the PCI input
clock, PCLK, must also be valid during this time. PCLK is only needed if the PCI module is being used.
If the DDR2 memory controller and the EMAC peripheral are not needed, CLKIN2 can be tied low and,
in this case, the POR pin must remain asserted (low) for a minimum of 256 CLKIN1 cycles after all
power supplies have reached valid operating conditions.

Within the low period of the POR pin, the following happens:
– The reset signals flow to the entire chip (including the test and emulation logic), resetting modules
that use reset asynchronously.
– The PLL1 controller clocks are started at the frequency of the system reference clock. The clocks
are propagated throughout the chip to reset modules that use reset synchronously. By default,
PLL1 is in reset and unlocked.
– The PLL2 controller clocks are started at the frequency of the system reference clock. PLL2 is held

in reset. Since the PLL2 controller always operates in PLL mode, the system reference clock and all the system clocks are invalid at this point.
– The RESETSTAT pin stays asserted (low), indicating the device is in reset.
3. The POR pin may now be deasserted (driven high).
When the POR pin is deasserted, the configuration pin values are latched and the PLL controllers
change their system clocks to their default divide-down values. PLL2 is taken out of reset and
automatically starts its locking sequence. Other device initialization is also started.
4. After device initialization is complete, the RESETSTAT pin is deasserted (driven high). By this time,
PLL2 has already completed its locking sequence and is outputting a valid clock. The system clocks of
both PLL controllers are allowed to finish their current cycles and then paused for 10 cycles of their
respective system reference clocks. After the pause the system clocks are restarted at their default
divide-by settings.
5. The device is now out of reset, device execution begins as dictated by the selected boot mode

Kind regard,

one and zero

0 Walter Maguire over 10 years ago in reply to one and zero

Prodigy 10 points

Hi All,

We have followed the above advice but still no joy using a 3rd party FMC board. We don't have access to PCI_EN line which is pulled high on the 3rd party board. Initially we thought the issue was due to the FPGA configuration IO states to pull high. We modified the design to make sure that the FPGA outputs at high impedance tri state. Still no joy.

On power up we have no clocks to the DSP as these are generated by the FPGA and we need to wait until the FPGA is configured and the associated clocking wizard IP is locked. Therefore I suspect the power to the TI chip is applied with no clocks. However, that been said the PORn and RESETn lines are held low until the clocks are locked, and then we initiate the entire PORn reset procedure as described above.

I wonder if the chip is locking up due to the clocks not being present when the power lines ramp up?

Regards

Walter

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C6455 restart or reload problem & EDMA3 efficiency