TMS320C6748: Use of McAsp fifo Dma to event ratio

Chris Coonan88

Part Number: TMS320C6748

I currently have a McAsp driver that works well if the WNUMEVT is set to 1.I have 1 serializer. When I change it to anything else, I get continuous RX/TX errors. I modified the edma bCnt value accordingly. What am I possibly doing wrong? Is there another setting that needs to be done?

Thank you.

over 6 years ago

0 Yordan Kovachev over 6 years ago

TI__Guru**** 161600 points

Which SDK version is this?

Best Regards,
Yordan

0 Chris Coonan88 over 6 years ago in reply to Yordan Kovachev

Prodigy 125 points

I inherited this code and cannot answer your question. All I have are a few C files for mcasp driver and mcasp-edma. I am hoping that you can highlight an area for me to investigate/debug. Something that I am missing.

0 Sahin Okur over 6 years ago in reply to Chris Coonan88

TI__Mastermind 27355 points

Hi Chris,

I'm assuming WNUMDMA is set to 1? What TX/RX errors are you getting? You can view the RSTAT & XSTAT registers to see if any flags have been set.

Also, have you already seen the following wiki? processors.wiki.ti.com/.../AM1x_Multichannel_Audio_Serial_Port_(McASP)_Throughput_and_Optimization_Techniques

0 Chris Coonan88 over 6 years ago in reply to Sahin Okur

Prodigy 125 points

WNUMDMA is set to 1.
I am getting ROVRN and XUNDRN errors.

RSTAT = 0x159

TSTAT = 0x179

Thanks.

0 Mark Mckeown over 6 years ago in reply to Chris Coonan88

TI__Mastermind 29210 points

Hi Chris,

Did you get this issue debugged?

What are the different values you are using for the EDMA?
Can you compare the rates of DMA interrupts?
In the DMA ISR also check the WLVL in WFIFOSTS. Are the errors constant or spurrious?

The buffer underrun and overrun errors sound like the FIFO is not getting serviced or setup correctly. Are you configuring the FIFO before rest of McASP registers? And configuring the McASP registers in the order outlined in 25.0.21.1.2 Transmit/Receive Section Initialization?

Buffer Underrun Error - Transmitter
A buffer underrun occurs when the serializer is instructed by the transmit state machine to transfer data from XRBUF[n] to XRSR[n], but XRBUF[n] has not yet been written with new data since the last time the transfer occurred.

Buffer Overrun Error - Receiver
A buffer overrun occurs when the serializer is instructed to transfer data from XRSR[n] to XRBUF[n], but XRBUF[n] has not yet been read by either the DMA or the DSP.

Regards,
Mark

0 Mark Mckeown over 6 years ago in reply to Mark Mckeown

TI__Mastermind 29210 points

Perhaps you can check how the old Starterware code setup the FIFO for reference.

http://www.ti.com/tool/starterware-dsparm

/**
 * \brief   Enables the Write FIFO for McASP. This shall be done before
 *          taking McASP out of Reset. First this API sets the FIFO parameters
 *          keeping the FIFO disabled. Then it enables the FIFO
 *
 * \param   baseAddr      Base Address of the McASP FIFO Registers.
 * \param   numTxSer      Number of Transmit Serializers to be used.
 * \param   minWdPerSer   The minimum number of words per serializer 
 *                        to be available in FIFO to issue a DMA event.
 *
 * \return  None.
 *
 **/
void McASPWriteFifoEnable(unsigned int baseAddr, unsigned int numTxSer, 
                          unsigned int minWdPerSer)
{
    HWREG(baseAddr + MCASP_FIFO_WFIFOCTL) = numTxSer | 
                                            ((minWdPerSer * numTxSer)
                                             << AFIFO_WFIFOCTL_WNUMEVT_SHIFT);

    /* The configuration is done. now set the enable bit */
    HWREG(baseAddr + MCASP_FIFO_WFIFOCTL) |= AFIFO_WFIFOCTL_WENA;
}

Regards,
Mark

0 Chris Coonan88 over 6 years ago in reply to Mark Mckeown

Prodigy 125 points

The issue is resolved. I simply needed to change the fifo configuration to Multi-slot Interlaced.

Chris

0 Mark Mckeown over 6 years ago in reply to Chris Coonan88

TI__Mastermind 29210 points

Hi Chris,

Thanks for sharing the resolution. What registers did you change to fix this issue?

Regards,
Mark

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TMS320C6748: Use of McAsp fifo Dma to event ratio