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TMS320C6747: Best dev. board for porting DSP from FPGA to TI processor..?

Part Number: TMS320C6747
Other Parts Discussed in Thread: PCM1802, TMDSOSKL137, OMAP-L137

Hi folks.  New here.  I'm thinking of porting my IP to Ti DSP from FPGA.

So I am looking at the simplest and easiest way to port a task presently in another product (Spartan3AN) over to a Ti DSP.  I want floating point capability, and easy transition from a demo board to my OEM product.  I'm looking for something that has 24bit AD/DA codec that I can re-purpose on my own board without re-inventing the code and drivers if possible.  I'm wondering if the TMDSOSKL137 would be the one for me to get.  What do you think?  Will I be able to get up and running my simple DSP code in/out of the codec fast and easy with this DSP and dev. board?  Looking forward to getting started.  

Cheers,

Bob

  • Hi,

    We're looking into this.

    Best Regards,
    Yordan
  • Hi Bob, that OSK is probably the way to go. The AIC3106 stereo codec on the board supports 24-bit audio, and we've got some basic analog loopback code.

    Is stereo good enough? If you need multichannel, please have a look at this daughter card:

    www.spectrumdigital.com/.../

    ADC is PCM1802, DAC is actually an AKM AK4588 combo codec (has DIR built in, as well). Both are 24-bit.

    Similar situation - we have some basic analog loopback code.
  • Thank you, Yordan, Tufino. Can an external clock be applied to the Codec on this dev. board? My Spartan3AN design uses a 24bit Codec clocked by an external 49.152MHz. clock. The FPGA 'drivers' take this external 49.152MHz. clock and generate the required signals and timing to read and write 48KHz. audio with the codec. Do you know if I will be able to recreate this configuration for audio clock on the TMDSOSKL137 ? Thanks. Cheers,
  • Hi Bob,
    I encourage you to check out the schematic, as it'll make this easier to follow:
    support.spectrumdigital.com/.../EVMOMAPL137_Schematics_RevD.pdf

    If the idea is to replace your FPGA with the TI DSP, then yes, this is essentially what we're already doing.

    Check out page 22 of the schematic. In this case, we've got a 24.576 MHz oscillator (U39) driving an MCLK into the AIC3106 codec (U38), and also into the AHCLKX1 pin on McASP1 (follow the T_AIC_MCLK net all the way back to sheet 2). McASP1 then takes this MCLK and divides it down to generate a bit clock (ACLKX1) and frame sync (AFSX1), and then drives those into the AIC3106 (back to sheet 22). This is a really common approach; often times we want to get some reference MCLK to the DSP and be able to divide it down depending on whether we are dealing with 48k or 96k, etc content.

    Close enough? If you want to keep that 49.152 MHz MCLK, you can probably find a pin-compatible oscillator at that rate and swap it out, but I suspect that all you care about is being able to get the right I2S clocks for 48 kHz operation, which you can do with the existing 24.576 MHz osc. If you actually want to feed whatever this external source is into the board, you could probably pull off U39 and wire something in.

    Thanks,
    Bobby
  • That's encouraging. Thanks, Bobby. 

    So if I understand, this evaluation board uses 24.576MHz. reference to generate sample rate of 48KHz., so if I were to swap in an external clock to replace the oscillator, at 24.152MHz. (slightly slower), then would I change the McASP or MCLK math, or configuration somewhere, to derive the same 48Khz. audio sample rate from the 24.152MHz. clock?

    To help outline what I need to do - if I need to, or it would be easier to do, I could change my external clock source to 24.576MHz. for 48KHz., as expected by the Ti board. So it all sounds good.  however, the high frequency clock on the Ti board is curiously only slightly different - can a range of input clock frequencies be used to obtain arbitrary audio sample rates by any chance? Or dev. board oscillator a tiny bit off? (49.152MHz. divided by 1024 gives 48KHz.) 

    This dev. board looks like the best choice I have found so far to get my design moved from FPGA into DSP, and then onto custom PCB product.  Now I just want to be sure I understand a little better.  Thank so much.  Cheers,

  • Hi, McASP only has integer clock dividers, so you won't be able to get the 48 kHz numbers that you want from 24.152 MHz.

    In the case of 24.576 Mhz, it looks like this:

    fs = 48 kHz
    bit clock = 64 fs for stereo I2S = 3.072 MHz.  It's 32-bit per slot (even if it's only 16- or 24-bit data, we deal in 32-bit words) * 2 slots (left and right).
    master clock = 512fs, so 4.576 MHz for 48 kHz. You can also do 256fs, 128fs, etc.  It depends on what MCLK:fs ratio is required by the codec, usually.

    Sometimes you can get some MCLK value to divide down to the sample rate, but you won't be able to get the bit clock with integer dividers.  For example, obviously you can get 48.0 MHz to divide down to 48 kHz, but you can't get it to divide down to 3.072 MHz for the bit clock.  This is why you'll usually see 24.576 MHz or 12.288 MHz crystals on audio designs, as they divide down cleanly to get you the bit clock and frame sync required for 48/96/192 kHz audio.


    I just want to make sure - do you actually want to use 24.152 MHz, or 49.152 MHz?  24.152 won't work, but 49.152 MHz works (2x24.576).  Basically as long as you can integer-divide down to fs and 64fs, you can use whatever MCLK you want as long as the AIC3106 is OK with it.  Its upper limit for MCLK is 50 MHz.

    Thanks,

    Bobby

  • Sorry, Bobby, my mistake.. I think I get it now - somehow I mistakenly read the Ti board to use 49.576 MHz. rather than the 24. 576 that it in fact uses.  

    So, to recap:

    My design on the Spartan3AN uses 49.152 (48,000 * 1024) which is exactly twice the master audio clk frequency of this Ti board. 

    Will it be a simple matter of changing a division of 512 to a division of 1014 to run the Ti board from twice the master audio clk frequency, somewhere in the drivers?

    If it isn't a trivial change of code, I have the option to change my external audio clock to 24.576MHz. - however this would require reworking my clock source and reprogramming OTP devices.  

    Thanks.

    Cheers,

    Bob

     

     

     

  • Hi Bob, OK, that makes sense.  Yes, it should be that easy. I haven't written software in a while, but it should be a trivial change.

    You'll actually be changing the divide value for the divider that sits between the mclk (AHCLKX1) and the bit block (ACLKX1) -- look for a bit field called CLKXDIV in the register ACLKXCTL.  The frame sync generator will take it from there and you'll get the 48kHz that you're looking for.  I suggest grabbing the TRM for OMAP-L137 and familiarizing yourself with McASP.  Look at section 26.0.21 for details on the clock and frame sync generators:
    www.ti.com/.../spruh92d.pdf

    Good luck!

    Bobby

  • Great. Looks good. Thanks, Bobby, and for the links to more info.