Hi,
We're working on a new design where we plan to hook up an ADC to the uPP port on the C6748. We plan on using the 456MHz part. I'd like to get clarification on the maximum clock input frequency we can drive in CHx_CLK when a channel is configured for input (receive).
In Table 6-117. Switching Characteristics Over Recommended Operating Conditions for uPP of the C6748 datasheet, it lists the maximum cycle time of 13.33ns for SDR mode when using 1.3V. That comes out to 75MHz.
But then in the C6748 TRM, it states the max allowed is CPU/4 which in the 456MHz CPU case would be 114MHz. I assume the datasheet overrides the TRM but we need clarification.
From the TRM
31.2.1.2 Receive Mode (Single Data Rate)
The channel requires an external clock to drive its CLOCK pin. The incoming clock is not divided, and its
maximum allowed speed is one fourth (¼) the device CPU clock speed.
