offset address | opcode | assembly instruction | |
00000000 | 07bf09c2 | SUB .D2 SP,24,SP | ; [B_D64P] |143| |
00000004 | 01a0aa28 | MVKL .S1 0x1c14154,A3 | ; [A_S674] |158| |
00000008 | 0180e0e8 | MVKH .S1 0x1c14154,A3 | ; [A_S674] |158| |
0000000c | 018c0264 | LDW .D1T1 *A3(0),A3 | ; [A_D64P] |158| |
00000010 | 6c6e | NOP 4 | ; [A_L674] |
00000012 | ac35 | STW .D2T1 A3,*SP(4) | ; [B_D64P] |158| |
00000014 | 01a0ac28 | MVKL .S1 0x1c14158,A3 | ; [A_S674] |159| |
00000018 | 0180e0e8 | MVKH .S1 0x1c14158,A3 | ; [A_S674] |159| |
00000020 | 018c0264 | LDW .D1T1 *A3(0),A3 | ; [A_D64P] |159| |
00000024 | 6c6e | NOP 4 | ; [A_L674] |
00000026 | cc35 | STW .D2T1 A3,*SP(8) | ; [B_D64P] |159| |
00000028 | 01a0ae28 | MVKL .S1 0x1c1415c,A3 | ; [A_S674] |160| |
0000002c | 0180e0e8 | MVKH .S1 0x1c1415c,A3 | ; [A_S674] |160| |
00000030 | 018c0264 | LDW .D1T1 *A3(0),A3 | ; [A_D64P] |160| |
00000034 | 6c6e | NOP 4 | ; [A_L674] |
00000036 | ec35 | STW .D2T1 A3,*SP(12) | ; [B_D64P] |160| |
00000038 | 01a0b028 | MVKL .S1 0x1c14160,A3 | ; [A_S674] |161| |
00000040 | 0180e0e8 | MVKH .S1 0x1c14160,A3 | ; [A_S674] |161| |
00000044 | 018c0264 | LDW .D1T1 *A3(0),A3 | ; [A_D64P] |161| |
00000048 | 00000000 | NOP 4 | ; [A_L674] |
00000048 | 01bc82f4 | STW .D2T1 A3,*SP(16) | ; [B_D64P] |161| |
I am going through the “TMS320C6000 CPU and Instruction Set Reference Guide, Literature Number: SPRU189F October 2000” and I am able to understand why these NOP instructions are there. Most of these NOP 4’s are there as there are 4 delay slots after a LDBU/LDW instruction which means it takes 4 cycles for the register to be completely loaded.
But I am not able to understand why different opcodes are there. From what I understood from the datasheet, NOP or NOP 1 should have an opcode of 00000000, NOP 4 should have an opcode of 00006000.
can any one please clarify why a different opcode is generated for same instruction.