C6000 Single Core DSP

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C6454
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  • Forum Post: c6454 GPIO HWI

    steve
    Hi, I am trying to use a GPIO signal as a HWI on a TMS320C6454 DSP. The HWI I created is never executed. I will try to explain what I am doing to set up the HWI. Let's say I'd like to use GP[6] rising edge for the HWI. In main(), I configured the GPIO registers as follows: GP[6] is set as...
    on Nov 11, 2008

  • Forum Post: [6454] Irregular Power Sequence Question

    TimHarron
    When powering up a C6454 device, suppose the power sequencing looks like this: - 3.3V comes up first - 1.25V comes up next - 1.8V comes up last However, the 1.25V rail rises from 0 – 800mV in about 100us, drops to 400mv as the power device starts up, then rises back up steadily to 1.25V after...
    on Apr 8, 2010

  • Forum Post: How can I write data to PC memory on PCI master mode ?

    Do Hyoung KIM
    Hello everybody I wants to exchange data between DSP and PC through the PCI bus. So I use the PCI master mode. And set the PCIADDSUB[0] to physical address that is PC physical address but I can’t see any data on 0x4000 0000 address with CCS. What is problems? PC physical address: 0x60f7000...
    on Oct 19, 2010

  • Forum Post: Re: c6454 in Master I2C boot

    Loc
    Unfortunately the C6454 PCI module needs a running clock to properly initialize after reset. For this use case, an external clock source needs to be fed to XIO2001 PCI bus clock input (CLK pin). Anyone of XIO2001 seven PCI bus clock output (CLKOUTn) can be used to drive the C6454 PCI clock (PCLK).
    on Nov 16, 2010

  • Forum Post: Re: whether EMIF SRE signal function, when EDMA source is a FIFO on 32 bits/sync EMIF (EDMA is AB sync, Acnt=4)

    houdp
    Hello Randy, Thanks for the reply. What I have tried: 1. EMIF-32bits FIFO software read - ok. 2. EMIF-32bits FIFO EDMA Asnyc mode read - ok. 3. EMIF-32bits FIFO EDMA Snyc mode AxB=1,2,4*1000 read - fail. 4. EMIF-32bits FIFO EDMA Snyc mode AxB=8,16,32*1000 read - ok. ECLKOUT, CE...
    on Dec 3, 2010

  • Forum Post: whether EMIF SRE signal function, when EDMA source is a FIFO on 32 bits/sync EMIF (EDMA is AB sync, Acnt=4)

    houdp
    H ello, W e meet a EDMA-EMIF-FIFO issue on C6454, could you give some explanation? My system: FPGA<----32bits/Sync EMIF--->DSP The EMIF timing during EDMA trans is attached. EMIF config: CE3 CE3CFG: 32bits, sync, CE_EXT=1, RD_BE_EN=1, R_ENABLE=1, W_LTNCY_ZEROCYCLE, R_LTNCY_THREECYCLE...
    on Nov 26, 2010

  • Forum Post: Re: C6454 PCI autoinitialization and PCI bus hang

    Torbjorn Bakke
    Thank you for getting back to me on this, it is much appreciated. I agree that if we switch to I2C boot mode for the initial boot, it may perhaps be possible to increase the I2C frequency for a subsequent pci boot. However, getting back to the initial issue which was related to starting with an unprogrammed...
    on Mar 29, 2012

  • Forum Post: C6454 PCI autoinitialization and PCI bus hang

    Torbjorn Bakke
    Hi, we are currently struggling with an issue related to PCI autoinitialization using an external 24C1024 eeprom connected to the C6454. The C6454 is connected through an XIO2001 PCIe bridge to a Patsburg (Sandy bridge) chipset on the other end. What we observe is that when the eeprom is correctly...
    on Mar 26, 2012

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