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TI Home » TI E2E Community » Support Forums » Digital Signal Processors (DSP) » C6000 Single Core DSP » C64x Single Core DSP Forum » All Tags » HPI
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C6000 Single Core DSP

Welcome to the C6000 Single Core DSP Section of the TI E2E Support Community. Ask questions, share knowledge, explore ideas, and help solve problems with fellow engineers. To post a question, click on the forum tab then "New Post".

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HPI
  • 6455
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Related Posts
  • Forum Post: Re: TMS320C6000 HPI

    BrandonAzbell BrandonAzbell
    Camila Nunes The device is TMS320C6202 DMA. A document I would suggest using is the TMS320C620x/C670x DSP Program & Data Memory Controller/DMA Controller . This will provide the high level architecture of the DMA and how it is hooked into the CPU memory system. The DMA on the C6202B has...
    on Dec 21, 2008
  • Forum Post: HPI control problem

    Vladimir Podosinov Vladimir Podosinov
    Hello, I am interfacing an ADC to the HPI bus on the TMS320C6455. I know that HPI is a slave peripheral, and that actually makes a lot of trouble for me, but unfortunately there is no other choice for parallel ADC as EMIF is already taken by other device. ADC provides it's own clock (40 MHz), so...
    on Oct 1, 2009
  • Forum Post: Re: C6457 EMIF-HPI Link

    Craig Neely Craig Neely
    Hi Brandon, Thanks for the reply. That's good news that the EMIFA port is 3.3V as it means I can go to the DM6437's HPI w/o level shifters. Are you certain on the GPIO port? I was guessing it was 1.8V as the Lyrtech schematics for the EVM have boot mode pull-ups to 1.8V on those pins for...
    on Oct 11, 2009
  • Forum Post: C6457 EMIF-HPI Link

    Craig Neely Craig Neely
    Hello, I'm designing a board around the C6457 processor and I can't find an important bit of info in any of the data sheets. Which bus voltage do the EMIFA, HPI, and GPIO peripheral ports use? 1.8V or 3.3V? I'm embarrassed to ask something so basic, but I've looked everywhere I...
    on Oct 11, 2009
  • Forum Post: Use multiplexed GP0[15:8] after HPI boot process

    Fabion et Fronk Fabion et Fronk
    Hello, we do have a question regarding the multiplexed GP0/HPI pins of the TMS320C6418 DSP. We are developing an universal DSP Board with this DSP and a MSP430F1481 microcontroller serving as host for this system. This µC should initialize the DSP via HPI16, whose pins are multiplexed with...
    on Oct 15, 2009
  • Forum Post: booting the tci6486

    albertburbea albertburbea
    Hi all OK, now we have the EMAC0 working, but the question is on a different topic I am trying to boot the tci6486 using the HPI port. I write all the code in the DSP memory, and then assert DSPINT according to TI documentation spruea7c. Guess what? It does not work. We translate the coff file...
    on Oct 27, 2009
  • Forum Post: Re: booting the tci6486

    albertburbea albertburbea
    Hi yes, i can do that. I added an assembler interrupt vector, that loads at 0x800000 (0x10800000 global space) and jumps to _c_int00, as we did in older DSPs. I am not sure if this was the right thing to do, I am not sure if the software is running yet. We also have a new issue: after issueing...
    on Oct 29, 2009
  • Forum Post: Re: booting the tci6486

    albertburbea albertburbea
    Hi yes, I do. Is it possible to connect to the board using CCS and avoid a halt on connect? I mean - while the DSP is running (or not...) , I connect the CCS and maybe break the program execution to see where I am stuck. Also, I wrote Tom that we have a new issue: after downloading and (maybe)...
    on Oct 29, 2009
  • Forum Post: C6747 HPI

    E2E_display_name_Mike E2E_display_name_Mike
    We are testing the HPI on the C6747 and are only having partial success. I believe I followed everything in the HPI user's guide needed for initialization. Here is what seems to work so far: The host device can write a value to Address read/write registers and read back this value. The host...
    on Feb 10, 2010
  • Forum Post: pullup on C6455's HPI Data

    Jimmy Setyo Jimmy Setyo
    I am using TMS320C6555, and I am connecting HPI bus to FPGA's I/O pins. Since there's no internal pullups on C6455's HD[31:0], am I required to put external pullups on HD[31:0] ? I couldn't find the answer in datasheet nor design checklist. The only thing that I found in the...
    on Sep 16, 2010
  • Forum Post: C6455 EMIF / C5510 HPI - master/slave race condition

    Derek Wilson Derek Wilson
    I'm using C6455 EMIF to connect to a C5510 HPI. All data transfer's working great, but I'm running into a race condition which I can't seem to figure out how to solve. Here's the setup: I've got a couple of ring buffers on both the C6455 and C5510 as well as a couple of memory...
    on Sep 14, 2010
  • Forum Post: First step in loading code over HPI on the C6416

    Andy Chernock Andy Chernock
    I have a customer that has a question about booting a C6416 The design contains a 6416 connected via HPI and EMIF to an FPGA and has 8 Mbytes of off chip SRAM. The part boots over HPI, and basically the question is...to use the 8 Mbytes of off chip SRAM for code storage my customer believes...
    on Dec 17, 2010
  • Forum Post: C6414T HPI Operation Question

    TommyG TommyG
    C6414T is interfaced to host with HCSn tied low. The HRDYn signal never goes high when host is reading from DSP except at RESET. Is it a requirement that HCSn transition High to Low for HRDY to change states? In SPRU578C, last paragraph of sec 3.7, it states that HCSn gates the HRDYn output. In other...
    on Feb 3, 2011
  • Forum Post: C6457 HPI Maximum Sustained Throughput

    TommyG TommyG
    According to data manual (SPRS582B, sec 7.12.3) it seems that tw(HSTBL) + tw(HSTBH) are the specifications that define how fast the interface can operate. The value for 1.2 GHz CPU is 25 ns or 40 MHz which in HPI32 mode gives 160 MB/sec theoretical maximum. Is this a correct interpretation? Is there...
    on Feb 4, 2011
  • Forum Post: regarding building hex file to load in boot mode through HPI

    anish menon anish menon
    Hi Does anyone know if there is any documentation or the method to build a hex file in code composer to load into the dsp in boot through HPI mode... im using a tms320c6455.. thank you
    on Jun 14, 2011
  • Forum Post: regarding endianness issue

    anish menon anish menon
    Hi I am using tms320c6455 simulator on code composer v4. I get the error as wrong endianness. I am working on the Chip support library. I included the correct lib file which is the one that ends with an e. for big endianness. I also have selected the device to be big endian. Any suggestions...
    on Jun 15, 2011
  • Forum Post: hpi boot mode procedure for c6455 ?

    anish menon anish menon
    Hi So I am performing the following steps, dont know if its right 1> setting the dsp reset to low from a host processor 2>setting the hpi boot mode through the pins 3> setting the dsp reset to a high 4>writing the code to the dsp internal ram memory 5> setting the...
    on Jun 23, 2011
  • Forum Post: loading the code and data sections on the ti c6455 chip

    anish menon anish menon
    Hi I wanted to boot the c6455 DSP from HPI from a host processor. I was confused on how to load the code and data sections hex values, that is should I place them in consecutive locations on internal memory or is there some other way? Thank you
    on Jun 20, 2011
  • Forum Post: How to boot a C6748 DSP ?

    Didier Lafond Didier Lafond
    Hello, we are using a L138 EVM board and CCSV5 for our future design, we plan to use a C6748 DSP and an ARM host processor link to host processor will be SPI and maybe HPI What is the best choice for booting DSP ? I understand that : To boot from SPI : - we have to use DSP SPI slave...
    on Mar 22, 2012
  • Forum Post: Interfacing C6414/C6416 to AT91SAM9G54 ARM

    rrlagic rrlagic
    Hello! I'd like to ask community advice on the following topic. We have rather old and fixed digital board with C6414/C6416. On EMIFA we have FPGA, CPLD, and USB chip. On EMIFB we have 3 parallel flash memory chips of 4MB each. They served as boot source and storage for FPGA images. Because...
    on Apr 7, 2012
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