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TMS320C6455 DSK
Related Posts

  • Forum Post: Re: EMIF clock on the external interface

    Vladimir Podosinov
    Hello Randy P, Thanks for the reply. I realize that EMIF is technically was designed for the external memory, but it seems to be suitable for this DAC operation too. So in terms of the ECLKOUT cycles, this is what I get: Pause in a continuous AWE clock is 5 uS, which is 60 asynch memory cycles...
    on Apr 22, 2010

  • Forum Post: Re: EMIF clock on the external interface

    Vladimir Podosinov
    Hi Randy, I am attaching the simple EMIF test file that I have made from the example provided with the DSK. Also I am including GEL file, because maybe it can shed some light. I have tested additional output pins, and here is what I have found: -CE2 oscillates at the same rate as AWE, that is 12...
    on Apr 26, 2010

  • Forum Post: Could it be possible to configure endianess in the PCI controller (TMS320C6455)?

    Francisco Aguilar
    Hello, We're working with TMS320C6455 and we're trying to configure PCI communication with one General Purpose Processor. The DSP is working in slave mode. Our configuration is the following: /* Configure PCI */ PCI_CSRMIR = 0x02200412; PCI_BAR0MSK = 0xFFFF0000; PCI_SLVCNTL = 0x00070001;...
    on Apr 26, 2010

  • Forum Post: PCI

    Adam Nieves
    Hey everyone, I'm looking for a PCI example for C6455. Does anyone have some information to share? Thanks in advance, Adam
    on May 31, 2010

  • Forum Post: C6455 VCP2 Viterbi Co-Processor - Soft decoding

    Miguel Barcenilla
    Hello, I need help about the soft decisions in the Viterbi Co-Processor (VCP2) of the DSP TSM320C6455. The input data to the module (called Branch Metrics) are always soft inputs, and the output data can correspond either to soft or hard decisions. The VCP2 User's Guide says that VCP2 can be configured...
    on May 20, 2010

  • Forum Post: Re: problems about C6455 chainning EDMA3 channels

    Thomas Young
    Dear Drew, Thank you for your advice! I want to chain channel 0 to channel 8 but failed. Here is channel 0 param set: ///////////////////////////////////////////////////////////////////////// myParamSetup.option = CSL_EDMA3_OPT_MAKE( CSL_EDMA3_ITCCH_DIS, \ CSL_EDMA3_TCCH_EN, \ CSL_EDMA3_ITCINT_DIS...
    on Jul 6, 2011

  • Forum Post: Re: problems about C6455 chainning EDMA3 channels

    Thomas Young
    Stefano， Thank you for your advice! I have seen the old discussions that really help me find the answer to the problem. My project fails because of the wrong handle of the channel. I used to think that the channelk setup param equals to the number of the channel. If the channel is N, then the...
    on Jul 8, 2011

  • Forum Post: Re: Mistakes about the DSK6455 edma chain example

    Thomas Young
    RandyP， Thank you for your advice! I have seen the old discussions between you and Stefano which really help me find the answer to the problem. My project fails because of the wrong handle of the channel. I used to think that the channel setup param equals to the number of the channel. If the...
    on Jul 15, 2011

  • Forum Post: 6455 memory map prevented read of target memory

    hu shushu
    hello, when I debug my process,I put a global variable in the watch window.At first i can read the value of the variable .BUT when i run some code then,i found i can't read the variable.I the watch window ,it displays that "memory map prevented read of target memory ".and i go on...
    on Mar 6, 2012

  • Forum Post: Re: C6455 EMIFA question

    hu shushu
    Hello, thank you RandyP I have read the old thread you have recomended to me.I still don't know why. I found that the CE2 EMIFA is connected to CPLD,and the CPLD has severial registers,and the registers have severial bits that can't be write ,and it is just what I observed of the...
    on Mar 17, 2012

  • Forum Post: AIS Format Support

    ixworks
    I can't find anything on the Primary Bootloader in C6455, C6457 support of AIS format. Has this format been discarded since C6424? Is there a new format that was created for the primary bootloader to read from start of flash (EMIF mode)? Is there a "fastest" method?
    on Mar 14, 2012

  • Forum Post: Re: C6455 EMIFA question

    hu shushu
    Hello, RandyP Sorry for that I don't know how to quote your questions in this Description.I use my owe way . They are 8 8bits registers of offsets from 0xA0000000 . I have got the expected behavior.I can write the bits that can be writen. I want to write the other addresses in...
    on Mar 19, 2012

  • Forum Post: c6455 systerm clock

    hu shushu
    hello, I'm now using DSP/BIOS CLK to generate a 100K HZ Square wave.I don't know whether the systerm CLOCK is 1G or others and the relation between PRD Register and Microseconds. Thank you!
    on Mar 21, 2012

  • Forum Post: NDK_BroadcastPacket_Transmission_Gives Error Value 13

    Infant Jesuraj
    Hi, I am using the TMS320C6455 EVM for my application development on NDK. I am able to transmit the unicast packets but when i try to transmit a broadcast packet, the send() function returns with a error value 13. Error value 13 indicates EACCES which is permission denied error. I am transmitting...
    on Mar 1, 2012

  • Forum Post: Re: 6455 EMIFA in synchronous mode

    hu shushu
    Thank you for your reply! I have tested the timing of the signal in the EMIFA and it seems all right . I have found a thread that the expert say we can't use synchronous mode in EMIFA to daughts card .but somebody in the group say that he can use the synchronous mode. Can you give me...
    on Mar 31, 2012

  • Forum Post: 6455 EMIFA in synchronous mode

    hu shushu
    Hello, I want to use EMIFA in synchronous mode in my 6455DSK.I connect my DSP to FPGA .I had create a synchronous FIfo in FPGA and FIfo can work well. I cnofigure the EMIFA in synchronous mode and I'm sure it is right. But it doesn't work and i can't read from the fifo and what I read...
    on Mar 30, 2012

  • Forum Post: Re: 6455 EMIFA synchronous read question

    hu shushu
    Hello, Thank you for your reply! I have build a test project in the FPGA to detect the data writen from DSP and I am sure that it is complete correctly. AND I also build a test project in the FPGA to send data to the DSP and I'm sure the data in the emifa interface is not 0xFFFFFFFF and...
    on Apr 12, 2012

  • Forum Post: Re: 6455 EMIFA synchronous read question

    hu shushu
    Hello, Thank for your reply!I am so glad to hear what you said! But I don't quite understand that you have mentioned "the 6455 datasheet error data".What is this? If possible ,can you tell me what I should pay attention to configuring the EMIFA in syn mode? Thank you!
    on Apr 12, 2012

  • Forum Post: Re: 6455 EMIFA synchronous read question

    hu shushu
    Hello, I have read the 6455 datasheet error data and I find it's not such helpful to me because i have payed attention to it before. Could you please pass your project to me to see if it's something wrong with my DSK6455?My email address is 1013424531@qq.com .I really need your help ...
    on Apr 13, 2012

  • Forum Post: 6455 EMIFA synchronous read question

    hu shushu
    Hello, I have a question that disturbed me for severial days; I use daughtercard to connect to a FPGA and I configure the EMIFA of CE3 in synchronous mode.I found that I can write data to the FPGA, BUT I cannot read data from the FPGA . I am sure I configure the CE5CFG register of EMIFA correctly...
    on Apr 6, 2012

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