I am implementing an algorithm. The following reference (below dot line) is about the similar algorithm using TI 6201. What it said seems multiplier costs more than addition. I have some programming in C for TI 6713. I remember that TI DSP multiplication can be done in one cycle. It needs more instruction fatch? How do you think about that? Thanks.
A so called Q-format representation consisting of 16
bits for both integer and fractional parts is employed
for the fixed point implementation. Overflow is
avoided via clipping. Reduced complexity is achieved
by avoiding division or multiplication operation even
for the lookups. Interval size is specified as the power
of two to replace multiplications with shift operations.
The context is confusing here, since this was originally posted in the C64x Forum, the question is about the C6713, the Tag is for the 6211, and you reference some unknown document about the C6201.
If you have some programming in C for the C6713, please compile it and run it and see if the performance is what you require.
I am not sure what else to discuss here. If you have more specific questions, please re-state your questions for the processor of choice and give us document references if you are asking what we mean in some TI document.
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