Hello,
We are using the deivce TMS320C6727B. As per design, three devices connected onto the same EMIF Bus viz. Flash(16-bit), FPGA(16-bit), SDRAM(32-bit).
Following are the two transfers on EMIF Bus,1) Application will be residing in the Flash and at Boot-up it needs to be transferred to SDRAM. And the code execution will be done from SDRAM. So the program access will be done by the CPU. This will use the bridge BR3 of the crossbar switch.2) Application needs to periodically transfer data from FPGA to SDRAM. This will be a two-stage transfer i.e. from FPGA data will be transferred to DSP internal memory and then from internal memory to SDRAM. This will use the bridge BR4 of the crossbar switch.
The EMIF Bus being common in both the transfers, will it cause any problems. We would like to know how that is there any bus arbitration that can help when these two transfers occur simultaneously as both the devices are connected onto same EMIF bus.
Is any similar implmentation being done earlier by anyone?Regards,Ashwin.
AshwinThe EMIF Bus being common in both the transfers, will it cause any problems.
AshwinWe would like to know how that is there any bus arbitration that can help when these two transfers occur simultaneously as both the devices are connected onto same EMIF bus.
-Tim
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Our scheme is to connect both Flash and FPGA on the ASYNC 16-bit interface with chip select CS2. SDRAM is connected on 32-bit SYNC interface on EMIF bus with chip select CS0.
Flash memory will be required only during the start, till the application program from Flash is copied to SDRAM. This process will happen only during Boot-up. After this FPGA will come into picture on the chip select-CS2. We have used one address line A20 to distinguish the access between FPGA anbd FLASH. During application execution, the data from FPGA needs to be transferred to SDRAM. Hence during Boot-up FLASH will be selected and during run-time, FPGA will be selected.
Currently we are trying to manage the data to be transfered from FPGA to SDRAM in the DSP internal 256k unified Program/data RAM itself. If the data fits in less than 256k then there is no need to transfer data from FPGA to SDRAM.
Hope this gives a fair idea about the system.
Regards,Ashwin.
Yes, this helps paint a better picture. With your setup I do not see any significant problems that you will run into. The copies between FPGA and SDRAM will probably not be extremely fast, but if your system can handle the transfer delays there should not be any other side effects I can see to deal with.